How-to generate dual-port (read/write) RAM with clock enables

Hi Gerhard,

thanks for clarification. I didn't clearly understand that Arria 10 still compiles correctly but Agilex 5 and Stratix 10 don't accept the setting. According to Agilex and Stratix 10 Embedded Memory User Guides, this is due to hardware differences, user guide suggests that emulated TDP dual clock mode is necessary to achieve Arria 10 compatible behaviour. Question is if above altera_syncram instantiation actually activates read input and output register clock enable driven by common enable signal.

To be sure, the behaviour should be verified in a hardware test setup. Simulation model might be partly incorrect.

Regards Frank