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GerhardCadek's avatar
GerhardCadek
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1 month ago

How-to generate dual-port (read/write) RAM with clock enables

Following Stratix® 10 Embedded Memory User Guide (2025.07.24) chapter 2.11.6 independent clock enables are supported for read/write clock mode input/output clock mode I start a "RAM 2-port" IP g...
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GerhardCadek's avatar
GerhardCadek
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25 days ago

Hi Richard,

Happy New Year to you.

Due to the holydays and some urgent projects it took a while until I was able to test your suggestion. The brief test result: It does not work.

I used a simulation (Altera Questa 22.1) of our 10Gbit Ethernet MAC and verified the existing 2-port RAMs dual-clock (Arria 10 with Quartus Standard 20.1.1) with read clock enables against the solution you proposed (Stratix 10 with Quartus Pro 25.3). The FIFO looses using the new RAMs even when using your proposed structure. data. The difference origins out of the fact that obviously just the output register is affected by the "rdoutclocken" while the old "rdclocken" also affected the input side.

Are there any ideas on that? For me either the documentation is wrong or the Platform Designer is buggy.

Regards