How-to generate dual-port (read/write) RAM with clock enables

Hi Frank,

yes I'll require both clock enables for read input and read outputs be active which is not available without errors form Stratix10, Agilex5 etc. Its no issue of Quartus Pro versus Quartus Standard. I have these RAMs successfully created for Arria10 using Quartus Pro 18.1 & 23.2.

This perfectly works as expected. Same settings but different technology (Stratix 10 and newer FPGAs) and I am not able to generate these RAMs

As mentioned I applied a patch to the generated netlist which at least works in simulation (and is accepted by Quartus during implementation). The DIFF shows the changes:

Left ist the modified netlist, right the original one generated by Quartus. Basically I "just" changed the CE attributes. I don't know whether this will reliably work in hardware.

Best regards

Gerhard