How-to generate dual-port (read/write) RAM with clock enables

Hi Gerhard,

I checked some possible RAM configurations with manual setting of clock_enable in direct altera_syncram instantiation, e.g. your above posted setup, but ENA input of PORTBADDR register appeared always unconnected (ENA driver greyed out) in Resource Property Viewer. Output register is in constrast driven by clock_enable1.

Thus I conclude, the feature isn't actually available for Stratix 10 and Agilex. Another question is if adressstall_b might be used for intended purpose? This would be possible if input clock_enable shall be only applied to address register.

Regards
Frank

P.S.: Same code gives this Resource Property View for Arria 10. ENA input is also driven by clock_enable1. PORTBRE ENA also driven, but shown further down.