How-to generate dual-port (read/write) RAM with clock enables

Hi Frank,
these RAMs are part of the Ethernet data path to the CPU. The RAMs implement the RX & TX FIFOs. On one side there is the line interface (MAC function) while on the other side there is the CPU interface. Both sides inherently require a different clock. Data on the MAC side is twice the MAC width; thus every other clock the pipeline needs to be hold. On the CPU side the data is transmitted in bursts. After every burst cycle the pipeline again has to be put on hold. This worked perfectly with older technologies until Arria10. Starting with Stratix10 something had been changed in the generation of the RAM. One cannot select the mode as described in the documentation.

BTW: I modified the generated RAM netlists for both simulation & synthesis. Using these modified netlists the simulation results are OK. Quartus also implements the design without errors. Currently I am trying to find a hardware setup where I can test the implementation of these modified netlists. But I definitely favor a solution without manual patches.

Regards
Gerhard