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GerhardCadek
Occasional Contributor
Occasional ContributorHow-to generate dual-port (read/write) RAM with clock enables
Following Stratix® 10 Embedded Memory User Guide (2025.07.24) chapter 2.11.6 independent clock enables are supported for read/write clock mode input/output clock mode I start a "RAM 2-port" IP g...
GerhardCadekOccasional Contributor
Occasional ContributorThere is the same issue for Agilex 5. Again the documentation states:
Independent clock enables are supported in the following clocking modes:• Read/write clock mode—supported for both read and write clocks.• Input/output clock mode—supported for the registers of both ports
RichardT_altera
Super Contributor
Super ContributorYou can use below setting to enable the wrclocken and rdoutclocken.
- Use different clock enables for registers. (only available on Dual Clock: use separate "read" and "write" clocks)
- Use clock enable for write input registers.
- Use clock enable for output registers.
Regards,
Richard Tan
- GerhardCadek
Hi Richard,
thank you for this tipp. I will try this approach right next week!
Regards
Gerhard Cadek
- RichardT_altera
Any update on this?
Regards,
Richard Tan
