Agilex3 dcio parsing issue with RSU
Dear support, I am facing with the following issue: Environment: Quartus prime pro 26.1.0 build 110 (03/26/2026) on windows 11 Target board: Agilex3C evaluation kit (non-hps) Cosigned SDM + Authentication enabled Quartus pfg config file attached (manual.pfg.txt) I can successfully program the flash (the rbf helper signed) via Quartus programmer so the generated jic image is there. When I power-cycle the board and check in configuration debugger the RSU status, I get the following picture: attached rsu_dcio_issue.png I tried to generate the boot.rbf: from sof with -o rsu_boot=ON without injecting sdm without signing the rbf from sof with -o rsu_boot=ON with injecting a signed sdm, with signing the rbf (and basically all the combination with/without signing) In all cases I get back this same issue. QSF file also attached. I validated if I can load from configuration debugger the 1) Factory image (entered base address) --> OK 2) P1 image --> OK 3) P2 image --> OK so it looks like the error is either in the tables or in the decision firmware image itself. The decision firmware.rbf image I signed with permission 0x6, the agilex3.zip with permission 0x1 Today I basically iterated through all the possible way and it still fails. If anyone has any idea where to debug it further (online help again not helping too much), please let me know. Since the issue happening at commands those were in the normal and security guideline and where there are not so much parameters I believe it is either: 1) qsf issue, i am missing some assignment or have false setting --> but which one?? 2) quartus sw issue Thank you for your help in advance! Kind regards, Peter
Compilation Error (138001) Write permission
Hi, I'm taking a course in FPGA design and is using Quartus Prime Lite 16.1 (Free) and constantly run into permission errors. The latest one is during compilation. Error (138001): Cannot write to directory C:/nnn/AlteraPrj/pipemultQP16_1/Schematic/incremental_db, which is required for storing incremental compilation results. I simply can't find where and how the permission is denied. I've added as much permission as I can in the security-tab in the folder option. Best Regards/ Anna-Karin
Quartus 26.1: quartus_asm triggers quartus_pfg despite disabled generation flags
Product: Quartus Prime Pro Edition Version: 26.1.0 Build 110 (03/26/2026) Component: Assembler (quartus_asm) / Programming File Generator (quartus_pfg) Environment: Linux Summary Running quartus_asm with programming file generation explicitly disabled still triggers an internal call to quartus_pfg. This secondary step fails non-deterministically, even when no inputs or environment variables change between runs. Expected Behavior When invoking: quartus_asm ... --set=GENERATE_PROGRAMMING_FILES=OFF --set=GENERATE_RBF_FILE=OFF quartus_pfg should not be invoked at all, or it should be strictly disabled / skipped internally Actual Behavior quartus_asm always invokes quartus_pfg, even with generation disabled. This then leads to quartus_pfg unpredictably succeeding or failing. See attached log file. This leads to inconsistent results across identical runs. Outcomes observed across runs: The attached log file shows exemplary the different outcome of successive runs with no changes in between. The order of these results are interchangeable as observed. 1. Success Quartus Prime Programming File Generator was successful. 0 errors 2. Corruption error Error (19192): File ..._hps_auto.sof is corrupted 3. Segmentation fault *** Fatal Error: Segment Violation ... Reproduction Run repeatedly without changing anything: quartus_asm <proj> --read_settings_files=on --write_settings_files=off -c <rev> --set=GENERATE_PROGRAMMING_FILES=OFF --set=GENERATE_RBF_FILE=OFF Impact Breaks reproducibility guarantees Causes intermittent CI failures Forces workarounds (retry logic, ignoring exit codes, etc.) Undermines trust in assembler output stage Suggested Fixes / Questions Why is quartus_pfg invoked when: GENERATE_PROGRAMMING_FILES=OFF GENERATE_RBF_FILE=OFF? Can this behavior be: disabled completely, or controlled via a strict flag? Is there a known issue with: HPS-related SOF post-processing Workarounds (partial) Re-running the same command sometimes succeeds Running quartus_pfg separately succeeds Ignoring exit codes is unsafe due to real corruption cases Conclusion quartus_asm appears to implicitly depend on quartus_pfg even when disabled, and that dependency is unstable. This behavior is first observed in Quarts 26.1. In 25.3 quartus_asm does not implicitly call quartus_pfg. At minimum, this should be documented; ideally, the invocation should be conditional or removable.
Reset Release IP for Agilex needs Stratix 10 device files installed!
Just ran into the problem that Quartus Prime Pro 26.1 did not find the reset release IP which internally is named: altera_s10_user_rst_clkgate The reason in my case was that I had installed the Agilex 3 and 5 devices only, but not the Stratix 10. As the name of the component implies Agilex lends it from Stratix 10. Altera please correct the dependency tables for the installation of Agilex devices to include the library altera_s10_user_rst_clkgate_1949 (and possibly others too).sudden crashes of my Quartus Prime during Synthesis/Fitter
During the implementation of my project from the Quartus Prime GUI (Start compilation), my tool sometimes crashes. A window opens with the message: "Quartus Prime Problem Report - Sorry! The Quartus Prime software quit unexpectedly.....". No specific cause of the error is given. omething similar happens when I start my implementation from a TCL script. Here, I receive further information about the cause: Internal Error: Sub-system: OPT, File: /quartus/synth/opt/opt_op_add.cpp, Line: 10225 new_iterm_a && new_iterm_b Stack Trace: 0x881bd: RTL_ADDER::shrink_iports + 0x28d (SYNTH_OPT) 0x8794b: RTL_ADDER::create_binary_adder + 0x68b (SYNTH_OPT) 0x830be: RTL_ADDER::restruct_adder_network + 0xefe (SYNTH_OPT) 0x807e3: RTL_ADDER::aggressive_adder_balancing + 0xa3 (SYNTH_OPT) 0x102356: RTL_SCRIPT::call_common_rtl_fns + 0x706 (SYNTH_OPT) 0x104402: RTL_SCRIPT::call_named_function + 0x4b2 (SYNTH_OPT) 0xff8fb: RTL_SCRIPT::process_script + 0x17eb (SYNTH_OPT) 0x52b4: RTL_ROOT::process_parallel_helper_script + 0x2c4 (SYNTH_OPT) 0x134f4: sgn_run_rtl + 0x194 (synth_sgn) 0x41eb: qsyn_execute_sgn + 0x2ab (quartus_map) 0x13fb5: QSYN_FRAMEWORK::execute_core + 0x1d5 (quartus_map) 0x1378c: QSYN_FRAMEWORK::execute + 0x2ec (quartus_map) 0x108ab: qexe_do_grunt + 0x10b (comp_qexe) 0x16e90: qexe_run + 0x310 (comp_qexe) 0x18012: qexe_standard_main + 0xb2 (comp_qexe) 0x1b94e: qsyn_main + 0x55e (quartus_map) 0x12208: msg_main_thread + 0x18 (CCL_MSG) 0x13b18: msg_thread_wrapper + 0x78 (CCL_MSG) 0x15f13: mem_thread_wrapper + 0x73 (ccl_mem) 0x11a41: msg_exe_main + 0xa1 (CCL_MSG) 0x2c957: __scrt_common_main_seh + 0x10b (quartus_map) I might be that no error appears when I try again. What could be the cause?
memory infer
in my project that base agilex7 fpga, I need to use bit mask memory. the bit mask memory rtl behavior as follow. as quartus only support byte mask memory, so I think quartus tool should use logic(ALM registers) implementation instead of M20K. However, the fitter technology map shows that the following rtl behaviors is mapping to the M20k, that cause rtl behavior is inconsistent with fitter netlist. is this quartus eda bug? always @(posedge clk) begin if (ram_wra) data[ram_addra] <= (data[ram_addra] ＆ ~ram_bwma) | (wrp_dina ＆ ram_bwma); end always @(posedge clk) begin if (ram_rdb) wrp_doutb <= data[addrb]; end
qsys-generate outputs Info as Error
Hi everybody, I implemented a CI pipeline for Quartus projects in Azure DevOps / TFS that also runs qsys-generate.exe. One of the first outputs, namely "Info: Parallel IP Generation is enabled." gets marked as an error: ##[error]2026.04.28.14:01:10 Info: Parallel IP Generation is enabled. That leads to a fail of the whole pipeline (even though everything is fine). I can solve this by redirecting stderr to stdout, by calling qsys-generate.exe with the argument "2>&1". But of course this would also "hide" real errors. Could this issue please be fixed at some time? Thanks, ThomasHow can I use Quartus Pro 25.1 sopc-create-header-files tool to generate a jtag master header file?
I am an engineer in Terasic, I am writting a tutorial for Agilex 5. I use Quartus Pro 25.1, there is a sopc-create-header-files in \quartus\sopc_builder\bin path, I want to generate a header file in Windows system.however, I couldn't use it in Win10 system. I tried it in Nios V command Shell: even I used Windows WSL: or in Windows PowerShell： Thanks for your advice. Doreen
