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We try to manually place a carry chain in the Agilex 5 FPGAs which consists of more than 40 LABs. When we place this carry chain using set_location_assignment, Quartus crashes during the placement phase whenever the carry chain is longer than 40 LABs. Is it expected that the carry chain cannot be made longer than 40 LABs in the Agilex 5 FPGAs? Crash was observed on Quartus 25.3 and Quartus 26.1 for the devices A5ED065BB32AE4S and A5ED013BB32AE4SCS. Internal Error: Sub-system: FLABS, File: /quartus/fitter/flabs/flabs_util.cpp, Line: 96 p_to_fill->next == FLABS_OPENdcfifo problem
In our project, we instantiate the parameterizable DCFIFO primitive provided by Altera. The design passes simulation verification without issues; however, mismatches occur between written and read data from the DCFIFO by signalTAP during board-level testing , which consequently causes driver loading failures. fpga device：agilex7 with quartus pro25.3 dcfifo wr_clk: 450M dcfifo rd_clk: 416M the instantiate example: is there better suggestion?
Synthesis error
I generated HDL file from qsys and did the compilation in Quartus. Following error log was found: Error(13224): Verilog HDL or VHDL error at altpcieav_256_rp_rxm_rdwr.sv(287): index 3 is out of range [31:5] for 'addr' Error(13224): Verilog HDL or VHDL error at altpcieav_256_rp_rxm_rdwr.sv(287): index 3 is out of range [31:5] for 'addr' Error(13224): Verilog HDL or VHDL error at altpcieav_256_rp_rxm_rdwr.sv(287): index 3 is out of range [31:5] for 'addr' Error(13224): Verilog HDL or VHDL error at altpcieav_256_rp_rxm_rdwr.sv(287): index 3 is out of range [31:5] for 'addr' Error(13224): Verilog HDL or VHDL error at altpcieav_256_rp_rxm_txctrl.sv(196): index 4 is out of range [1:0] for 'tx_data' Error(13224): Verilog HDL or VHDL error at altpcieav_256_rp_txs.sv(196): index 95 is out of range [65:0] for 'rx_fifo_data' Error(13224): Verilog HDL or VHDL error at altpcieav_256_rp_app.sv(597): index 257 is out of range [71:0] for 'rx_fifo_dataq' Error(16851): Verilog HDL error at udh_en0.sv(127): formal port avs0 of type avlmm_ifc' from library 'function_enet_20 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191 Error(16851): Verilog HDL error at udh_en0.sv(125): formal port avs1 of type avlmm_ifc' from library 'function_enet_20 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191 Error(16851): Verilog HDL error at udh_en0.sv(123): formal port avs2 of type avlmm_ifc' from library 'function_enet_20 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191 Error(16851): Verilog HDL error at udh_en0.sv(122): formal port avs3 of type avlmm_ifc' from library 'function_enet_20 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191 Error(16851): Verilog HDL error at udh_en0.sv(121): formal port avm0 of type avlmm_ifc' from library 'function_enet_20 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191 Error(16851): Verilog HDL error at udh_en0.sv(119): formal port mdio_r of type mdio_ifc' from library 'function_enet_20 does not match with actual type mdio_ifc' from library 'altera_work Error(16851): Verilog HDL error at udh_en0.sv(120): formal port mdio_s of type mdio_ifc' from library 'function_enet_20 does not match with actual type mdio_ifc' from library 'altera_work Error(16851): Verilog HDL error at udh_en0.sv(118): formal port mdio_t of type mdio_ifc' from library 'function_enet_20 does not match with actual type mdio_ifc' from library 'altera_work Error(16851): Verilog HDL error at hssl_i.sv(130): formal port avs of type avlmm_ifc' from library 'function_hssl_20 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191 Error(16851): Verilog HDL error at hssl_i.sv(127): formal port avm0 of type avlmm_ifc' from library 'function_hssl_20 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191 Error(16851): Verilog HDL error at hssl_i.sv(128): formal port gmii_r of type gmii_ifc' from library 'function_hssl_20 does not match with actual type gmii_ifc' from library 'function_enet_20 Error(16851): Verilog HDL error at hssl_i.sv(129): formal port gmii_s of type gmii_ifc' from library 'function_hssl_20 does not match with actual type gmii_ifc' from library 'function_enet_20 Error(16851): Verilog HDL error at hssl_i.sv(131): formal port gmii_t of type gmii_ifc' from library 'function_hssl_20 does not match with actual type gmii_ifc' from library 'function_enet_20 Error(16851): Verilog HDL error at hssl_i.sv(125): formal port mdio_r of type mdio_ifc' from library 'function_hssl_20 does not match with actual type mdio_ifc' from library 'altera_work Error(16851): Verilog HDL error at hssl_i.sv(126): formal port mdio_s of type mdio_ifc' from library 'function_hssl_20 does not match with actual type mdio_ifc' from library 'altera_work Error(16851): Verilog HDL error at hssl_i.sv(124): formal port mdio_t of type mdio_ifc' from library 'function_hssl_20 does not match with actual type mdio_ifc' from library 'altera_work Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(380): formal port gmii0 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20 Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(382): formal port gmii1 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20 Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(377): formal port gmii2 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20 Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(378): formal port gmii3 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20 Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(374): formal port gmii4 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20 Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(376): formal port gmii5 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20 Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(372): formal port gmii6 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20 Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(373): formal port gmii7 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20 Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(370): formal port gmii8 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20 Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(371): formal port gmii9 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20 Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(366): formal port gmii10 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20 Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(367): formal port gmii11 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20 Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(391): formal port avs0 of type avlmm_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191 Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(390): formal port avs1 of type avlmm_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191 Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(387): formal port avs2 of type avlmm_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191 Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(386): formal port avs3 of type avlmm_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191 Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(389): formal port avs4 of type avlmm_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191 Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(388): formal port avs5 of type avlmm_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191 Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(383): formal port avs6 of type avlmm_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191 Error(16186): Can't elaborate top-level user hierarchy Error: Flow failed: Error: Quartus Prime Synthesis was unsuccessful. 65 errors, 191 warnings Error: Peak virtual memory: 1041 megabytes Error: Processing ended: Wed Sep 23 11:02:52 2026 Error: Elapsed time: 00:01:58 Error: System process ID: 23412 Error(293001): Quartus Prime Full Compilation was unsuccessful. 67 errors, 191 warnings It seems the instantiated avlmm(for instance) is trying to map to the same module in altera_work which gneerates this error. How do i solve it?How to organize a shared cache for qsys systems?
I have written a system to generate command lines and scripts/templates for various EDA tools. This will let me share the same same design across different implementations. The designs typically reside in a git (or some other VC) repository. For Altera IP's only the *.ip is kept in the git repository. The cache tag is generated from a hash of the content of the *.ip and the Quartus version used as this uniquely defines a single *.ip file. The build script will copy the '*.ip' file and run qsys-generate in the $cache/$tag location which will be added to the IP_FILE in the tcl build script. The next time the same Quartus version and same *.ip file is used it's referenced by the IP_FILE variable. This works pretty well. Putting the *.qsys itself into a similar structure works too. But distributing the *.ip and *.qsys children of the parent.qsys in the same cache seem to be problematic as the parent.qsys logicalView XML tag seem to contain a partial relative sub-path. Is there a way to make sure that only references to the child.ip or child.qsys will be present in the parent.qsys so that it can be located by the full absolute path specified in the IP_FILE? Also how are *_hw.tcl files located and what type of references and relations between these and their respective *.ip and/or *.qsys files are stored in these files? Or is the only solution to copy the full tree structure of the qsys into the cache and hash its full content? BTW I'm using Linux only.
