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New Contributor

2 days ago

fanout issue

now I develop a project with agilext7 FPGA, the sysclk is 416MHz. the project has still WNS=-500ps TNS=-5000ns violation. from the fitter duplication summary report below, we can see that the mos...

Compilation

Timing

RichardT_altera

Super Contributor

4 hours ago

You might need to manually duplicate the register to reduce the fan-out. Currently we don't have a global assignment that can set the max fan-out for all non-global signals.
Checkout the user guide below:
https://docs.altera.com/r/docs/683641/25.3.1/quartus-prime-pro-edition-user-guide-design-optimization/duplicate-registers-for-fan-out-control

Regards,
Richard Tan

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fanout issue

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