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Timing models don't match measured delays
I am working with an Agilex 7 I-series device in Quartus Prime Pro 25.3. The device is fully supported by that QPP version and has final timing models. Since I am working with precise timing, I need to find out the propagation delay from internal clock to output on a pin with as good precision as possible. I am trying to use the Timing Analyzer (TA) to do this. The results do not match my expectations though. The TA reports paths for five operating conditions for this device: fast/vid1/100C, fast/vid1a/100C, fast/vid1a/0C, slow/vid1b/100C and slow/vid1/100C. My expectation is that one of them corresponds to the shortest propagation delay (used for hold analysis) and one the longest (used for setup analysis) and that my measured delay should therefore fall somewhere between these extremes. It does not. To test this, I have added two registers to my design, both clocked by the same clock, both toggling at every clock edge. I have instructed Quartus to preserve these and don't merge them. These two registers drive two outputs that I can measure on the board. Then I control the placement of the two registers to get different propagation delay to their pins. I start out by calibrating the setup. Placing the two registers in the same LAB close to the relevant I/O bank results in very nearly the same path delay to both pins according to the TA. As expected, I also measure a very small difference between the edges (around 100 ps). This shows that there is no significant difference between the board traces or measurement cables. Then I move one of the registers a bit, 271 LABs in the X direction to be exact. According to the TA, this design should have the following propagation delay differences between the pins for the five operating conditions: Fast vid1 100C 3.134 ns Fast vid1a 100C 3.138 ns Fast vid1a 0C 2.795 ns Slow vid1b 100C 3.028 ns Slow vid1 100C 3.011 ns However, I measure just 2.32 ns. This is lower than even the 0C model, which must be the fastest timing that is used to guarantee hold timing. How can this be?retiming issue
we develop a project with agilex7 fpga and using quartus pro 25.3 version. now we fix timing by analyze the retiming report. we see the following retiming restriction: But the register GEN_REG_INUT.R_DATA[0][0] is directly driven by quartus hyper register, and it has no power up value and no sync reset. the retiming critical path as follow: -------------------------------------------+ ; Critical Chain Details ; +--------------------------+-------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Info ; Register ; Register ID ; Element ; +--------------------------+-------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Power-up Restriction ; ALM Register ; #1 ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0] ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]|q ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~LAB_RE_X221_Y195_N0_I99 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~R1_X221_Y195_N0_I10 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~C4_X220_Y191_N0_I11 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~LOCAL_INTERCONNECT_X220_Y191_N0_I26 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~BLOCK_INPUT_MUX_PASSTHROUGH_X220_Y191_N0_I35 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~LAB_RE_X220_Y191_N0_I39 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn|dataf ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn|combout ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~cw_la_lab/lab_lut6outt[4] ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_LAB_RE_X220_Y191_N0_I138 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C1_X220_Y190_N0_I17 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R1_X220_Y190_N0_I16 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X208_Y190_N0_I2 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X196_Y190_N0_I2 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X195_Y182_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X195_Y174_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X184_Y174_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X172_Y174_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X160_Y174_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X148_Y174_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X136_Y174_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X135_Y166_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X135_Y158_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X135_Y150_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X135_Y142_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X135_Y134_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X124_Y134_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X123_Y126_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X123_Y118_N0_I0 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R0_X123_Y118_N0_I2 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R2_X124_Y118_N0_I15 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R1_X126_Y118_N0_I31 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C1_X126_Y118_N0_I30 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C1_X126_Y119_N0_I30 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_LOCAL_INTERCONNECT_X126_Y120_N0_I61 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_BLOCK_INPUT_MUX_PASSTHROUGH_X126_Y120_N0_I80 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_LAB_RE_X126_Y120_N0_I82 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg|x_pe_pkg_pkt_pack|pack_data_padding_cross~xtophalf/xale2/xcw_ml_le_regctrl/xcw_la_le_regctrl_reg/sclr_out ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg|x_pe_pkg_pkt_pack|x_pack_data_shifter|bcnt[4]|sclr ; Long Path (Critical) ; ALM Register ; #2 ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg|x_pe_pkg_pkt_pack|x_pack_data_shifter|bcnt[4] ; why quartus report the retiming restriction?fanout issue
now I develop a project with agilext7 FPGA, the sysclk is 416MHz. the project has still WNS=-500ps TNS=-5000ns violation. from the fitter duplication summary report below, we can see that the most of number of duplicates is 4, how can we improve the number of duplicates to further to reduce fanout and congestion? quartus provides the GLOBAL_SIGNAL_PROMOTION_FANOUT_THRESHOLD setting, which the default is 50. In my project many signal fanout exceed 50, but I doesn't think the signals are being routed global network. so for non-global high fanout signals, what should I do？manually duplicating many high-fanout nets in the RTL is not practical.
