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annamalairaj's avatar
annamalairaj
Icon for New Contributor rankNew Contributor
20 days ago

Minimum pulse width violation on EMIF-HPS

We are observing Minimum pulse width summary violation on three clocks in EMIF. Snapshots of Minimum pulse width violation on each of these clocks are attached. 

Quartus version: 25.1.1 

targeted FPGA: AGFB027R24C2E3V

Please share your suggestions.

Timing

2 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    20 days ago

    Hello,

     

    I have a few questions below, please help to provide your feedback.

     

    1. Can you share the connection of the EMIF HPS IP in Platform Designer?
    2. What is the clock frequency you set in EMIF HPS IP?
    3. Is there any SDC has been set to target this clock?
    4. Is there any other IP than EMIF HPS IP in IO Bank 3C and 3D?
    5. Are you sharing the reference clock source for EMIF HPS IP?

     

     

    Regards,

    Adzim