Forum Discussion

annamalairaj's avatar
annamalairaj
Icon for New Contributor rankNew Contributor
7 months ago

Minimum pulse width violation on EMIF-HPS

We are observing Minimum pulse width summary violation on three clocks in EMIF. Snapshots of Minimum pulse width violation on each of these clocks are attached. 

Quartus version: 25.1.1 

targeted FPGA: AGFB027R24C2E3V

Please share your suggestions.

Timing

6 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    7 months ago

    Hello,

     

    I have a few questions below, please help to provide your feedback.

     

    1. Can you share the connection of the EMIF HPS IP in Platform Designer?
    2. What is the clock frequency you set in EMIF HPS IP?
    3. Is there any SDC has been set to target this clock?
    4. Is there any other IP than EMIF HPS IP in IO Bank 3C and 3D?
    5. Are you sharing the reference clock source for EMIF HPS IP?

     

     

    Regards,

    Adzim

    • annamalairaj's avatar
      annamalairaj
      Icon for New Contributor rankNew Contributor
      30 days ago

      Hi AdzimZM_Altera​ 

      Sorry for the delayed response, and thanks for your patience. I wasn't able to follow up earlier. Regarding your questions:

      1. Can you share the connection of the EMIF HPS IP in Platform Designer?
        • Attached the image (emif_hps.png).
      2. What is the clock frequency you set in EMIF HPS IP?
        • 1200 MHz 
      3. Is there any SDC has been set to target this clock?
        • No.
      4. Is there any other IP than EMIF HPS IP in IO Bank 3C and 3D?
        • No, IO Bank 3C and 3D are dedicated only for EMIF HPS IP.
      5. Are you sharing the reference clock source for EMIF HPS IP?
        • No, we are not sharing this clock with any other blocks.
  • annamalairaj's avatar
    annamalairaj
    Icon for New Contributor rankNew Contributor
    16 days ago

    Hi AdzimZM_Altera​ 

    I have used Superior Performance with Maximum Placement Effort performance option and also tried the EMIF document optimize timing method by updating the Placement Effort Multiplier to 2 still same violation is observed.

    I have also attached the HPS subsystem files. 

    • AdzimZM_Altera's avatar
      AdzimZM_Altera
      Icon for Regular Contributor rankRegular Contributor
      14 days ago

      hi annamalairaj 

       

      I make hps_subsys as a top level, set the hps bridge as virtual pin and compile the design.

      I don't get the timing violation as you see.

      Can you try that from your end?