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7 months ago

Minimum pulse width violation on EMIF-HPS

We are observing Minimum pulse width summary violation on three clocks in EMIF. Snapshots of Minimum pulse width violation on each of these clocks are attached. Quartus version: 25.1.1 targeted F...

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7 months ago

Hello annamalairaj,

Do you have any feedback in this thread?

Regards,

Adzim

annamalairaj
New Contributor
30 days ago
Hi AdzimZM_Altera
Sorry for the delayed response, and thanks for your patience. I wasn't able to follow up earlier. Regarding your questions:
Can you share the connection of the EMIF HPS IP in Platform Designer?
Attached the image (emif_hps.png).
What is the clock frequency you set in EMIF HPS IP?
1200 MHz
Is there any SDC has been set to target this clock?
No.
Is there any other IP than EMIF HPS IP in IO Bank 3C and 3D?
No, IO Bank 3C and 3D are dedicated only for EMIF HPS IP.
Are you sharing the reference clock source for EMIF HPS IP?
No, we are not sharing this clock with any other blocks.
- AdzimZM_Altera
  Regular Contributor
  28 days ago
  Hi annamalairaj,
  
  Can you also share the hps subsystem qsys file?
  
  I tried to replicate the issue. So far do not able to see the timing violation within the HPS EMIF clock and HPS.
  
  Can you try use one of the performance option from the compiler settings?
  
  In Quartus goto: Assignments -> Settings -> Compiler Settings.
  
  You may refer to EMIF document to optimize timing here:https://docs.altera.com/r/docs/683216/23.2/external-memory-interfaces-agilextm-7-f-series-and-i-series-fpga-ip-user-guide/optimizing-timing
  
  Regards,
  
  Adzim