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WFH's avatar
WFH
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22 days ago

Lisence issue when running .do script

Hello,

I am a beginner using the Questa FPGA starter edition for practicing SystemVerilog coding.

I downloaded the 2025.2 Version and obtained the fix lisence according to NIC ID (my PC's Ethernet adapter's MAC address). And I set accordingly the environment variable(LM_LICENSE_FILE and SALT_LICENSE_SERVER) pointing to the .dat file. The software Questa run successfully.

But when I want to use a .do script to run a simple SV simulation, the process failed and showed as attachment 1.

The programm is simple and I believe it has no advanced grammar (attachment 2 and 3), but it still failed.

Is that the limination of Starter Edition or problem about lisencing?

Thank you in advance.

 

Installation & Licensing

9 Replies

  • BCuze's avatar
    BCuze
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    22 days ago

    How is your queue declared ?

    Be aware that if you want to use the SV randomization, you need an advanced version of Questa (to use the Solver) and neither Starter nor OEM Editions do have this. OTOMH that's what the svverification license feature is enabling. $urandom (Verilog) etc will work, but not the SV randomization methods.

    • WFH's avatar
      WFH
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      22 days ago

      Hello,

      the declaration of the queues is like this:

      bit [7:0] loc [$];

      bit [7:0] golden[$];

      And I did not use any method like randomization but $urandomm just as showed in attachment 2 and 3.

      If I change the "program" to "module", the code runs. Is the Starter Edition unable to use the SV keywords like "program"?

    • BCuze's avatar
      BCuze
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      21 days ago

      I was precisely wondering about the program block.
      So you have the proper workaround it seems :-)

      Just out of curiosity : what was your motivation for using a program block ?
      I have been teaching SV for as long as it exists and we even removed the chapter about the program block...
      I remember that it was (in the early days of SV at least) a source of trouble in the SV scheduler implementation (and a source of non determinism across tools).

      • WFH's avatar
        WFH
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        21 days ago

        Thank you:)

        I am beginner for learning SV for verification. In my Textbook it introduces the Program block that it is used to seperate the software block(Input stimulus written in Program) and hardware block(DUT). 

        Is that out of date?