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UserID4331231's avatar
UserID4331231
Icon for Occasional Contributor rankOccasional Contributor
8 months ago

JTAG timing violations

 

Hello

Following are my project details

LAST_QUARTUS_VERSION "25.1.0 Pro Edition"
DEVICE AGIB027R29A1E2VC
 "Agilex 7"

in SDC file - I have 

create_clock -name {altera_reserved_tck} -period 30 [get_ports {altera_reserved_tck}]
set_clock_groups -asynchronous -group {altera_reserved_tck}

I am getting timing violation in JTAG path (n/a domain). Lets ignore IOPLL domain violations for this thread.

Attached is the timing compilation results for "n/a" path. I need your help in resolving JTAG timing violations. I tried to refer earlier threads on the "JTAG violations" but its not quite helping so opening this thread.

thanks

 

  

 

 

Compilation
Timing

6 Replies

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    8 months ago

    You can add the JTAG signal Constraints template in the Quartus software.
    In the Quartus, Create a new sdc file, in the text editor, right-click > Insert Template... > Timing Analyzer > SDC Cookbook > JTAG Signal Constraints > Insert. 

    Regards,
    Richard Tan

  • UserID4331231's avatar
    UserID4331231
    Icon for Occasional Contributor rankOccasional Contributor
    8 months ago

    I added another SDC file containing JTAG signal Constraints template but I still have JTAG violation 

    the first SDC have 

    create_clock -name {altera_reserved_tck} -period 30 [get_ports {altera_reserved_tck}]
    set_clock_groups -asynchronous -group {altera_reserved_tck}

    and the second SDC have JTAG Signal Constraints as generated by steps mentioned above.

     the slack increased to -48.914 as it added Data required time -44.688 Vs in previous run it was reported as 0.

     

     

  • UserID4331231's avatar
    UserID4331231
    Icon for Occasional Contributor rankOccasional Contributor
    8 months ago

    I have created another SDC file with "JTAG Signal Constraints" template added.

    The original SDC already have 

    create_clock -name {altera_reserved_tck} -period 30 [get_ports {altera_reserved_tck}]
    set_clock_groups -asynchronous -group {altera_reserved_tck}

     

    still getting JTAG path violation as aseen in the screenshot. the slack increased to -48.914 as  Data Required Time  of ~44 was added Vs the last run. 

     

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    8 months ago

    Please kindly help to share your design (Project > Archieve Project) for further investigation. 

    Regards,
    Richard Tan

    • RichardT_altera's avatar
      RichardT_altera
      Icon for Super Contributor rankSuper Contributor
      8 months ago

      You might try reducing the TCK clock rate to 16 MHz:
      https://www.intel.com/content/www/us/en/docs/programmable/683719/current/changing-the-tck-frequency.html

      Which device are you using?

      Without the design files, debugging will be more difficult.

      Regards,
      Richard Tan