JTAG timing violations

You can add the JTAG signal Constraints template in the Quartus software.
In the Quartus, Create a new sdc file, in the text editor, right-click > Insert Template... > Timing Analyzer > SDC Cookbook > JTAG Signal Constraints > Insert. 

Regards,
Richard Tan

I added another SDC file containing JTAG signal Constraints template but I still have JTAG violation 

the first SDC have 

create_clock -name {altera_reserved_tck} -period 30 [get_ports {altera_reserved_tck}]
set_clock_groups -asynchronous -group {altera_reserved_tck}

and the second SDC have JTAG Signal Constraints as generated by steps mentioned above.

 the slack increased to -48.914 as it added Data required time -44.688 Vs in previous run it was reported as 0.

I have created another SDC file with "JTAG Signal Constraints" template added.

The original SDC already have 

create_clock -name {altera_reserved_tck} -period 30 [get_ports {altera_reserved_tck}]
set_clock_groups -asynchronous -group {altera_reserved_tck}

still getting JTAG path violation as aseen in the screenshot. the slack increased to -48.914 as  Data Required Time  of ~44 was added Vs the last run. 

Please kindly help to share your design (Project > Archieve Project) for further investigation. 

Regards,
Richard Tan

I cant share project at it has many confidential IPs