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UserID4331231's avatar
UserID4331231
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8 months ago

JTAG timing violations

  Hello Following are my project details LAST_QUARTUS_VERSION "25.1.0 Pro Edition" DEVICE AGIB027R29A1E2VC  "Agilex 7" in SDC file - I have  create_clock -name {altera_reserved_tck} -perio...
Compilation
Timing
UserID4331231's avatar
UserID4331231
Icon for Occasional Contributor rankOccasional Contributor
8 months ago

I cant share project at it has many confidential IPs

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    8 months ago

    You might try reducing the TCK clock rate to 16 MHz:
    https://www.intel.com/content/www/us/en/docs/programmable/683719/current/changing-the-tck-frequency.html

    Which device are you using?

    Without the design files, debugging will be more difficult.

    Regards,
    Richard Tan