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UserID4331231's avatar
UserID4331231
Icon for Occasional Contributor rankOccasional Contributor
8 months ago

JTAG timing violations

  Hello Following are my project details LAST_QUARTUS_VERSION "25.1.0 Pro Edition" DEVICE AGIB027R29A1E2VC  "Agilex 7" in SDC file - I have  create_clock -name {altera_reserved_tck} -perio...
Compilation
Timing
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
8 months ago

You can add the JTAG signal Constraints template in the Quartus software.
In the Quartus, Create a new sdc file, in the text editor, right-click > Insert Template... > Timing Analyzer > SDC Cookbook > JTAG Signal Constraints > Insert. 

Regards,
Richard Tan