TimeQuest Question Relating PLL

I have a design on a DE23-lite board. I use the onboard 50 MHz clock to feed a PLL set to 150 MHz. All registers clock on the PLL. I_clk is the 50 MHz clock.

I use the following rule:

create_generated_clock -name clk_pll -source [get_ports {I_clk}] -multiply_by 3 [get_pins {pll0|iopll_0|tennm_ph2_iopll|out_clk[0]}]

(Yes, the PLL output has that name)

Now TimeQuest complains:

No paths exist between clock target "pll0|iopll_0|tennm_ph2_iopll|out_clk[0]" of clock "clk_pll" and its clock source. Assuming zero source clock latency.

So I looked up the PLL input clock. But if I write:

create_generated_clock -name clk_pll \
    -source [get_pins {pll0|iopll_0|tennm_ph2_iopll|ref_clk0}] \
    -multiply_by 3 \
    [get_pins {pll0|iopll_0|tennm_ph2_iopll|out_clk[0]}]
  

the setup slack on I_clk is -7 ns, but no register clocks on this clock.

So what to do?