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jesseopdenbrouw's avatar
jesseopdenbrouw
Icon for New Contributor rankNew Contributor
9 months ago

TimeQuest Question Relating PLL

I have a design on a DE23-lite board. I use the onboard 50 MHz clock to feed a PLL set to 150 MHz. All registers clock on the PLL. I_clk is the 50 MHz clock. I use the following rule: create_genera...
Timing
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
9 months ago

Something is failing timing in the input clock domain, not the clock itself.  You need to generate timing reports and understand what is failing timing.  You should also generate an unconstrained paths report to make sure your design is considered fully constrained for timing.  You might want to check the user guide (https://www.intel.com/content/www/us/en/docs/programmable/683243/25-3/faq.html) and training (https://learn.altera.com/learn/learning-plans/17/timing-analysis-with-the-alterar-quartusr-prime-pro-software) if you're not familiar with how to perform timing analysis and closure.

You could also try posting your .sdc file here.