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jesseopdenbrouw's avatar
jesseopdenbrouw
Icon for New Contributor rankNew Contributor
9 months ago

TimeQuest Question Relating PLL

I have a design on a DE23-lite board. I use the onboard 50 MHz clock to feed a PLL set to 150 MHz. All registers clock on the PLL. I_clk is the 50 MHz clock. I use the following rule: create_genera...
Timing
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
9 months ago

Providing the design will help us better understand what is going wrong.
Currently, a .qar file cannot be attached in the forum (Work in Progress). ZIP file attachments are also not supported as they may pose security risks.
For now, please consider sending the design file and the SDC file so that I can try to reproduce the issue.
Additionally, please review the recommendations mentioned by sstrell first. If you are unable to resolve the issue, then share the design files.

Regards,
Richard Tan