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jesseopdenbrouw's avatar
jesseopdenbrouw
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7 days ago

TimeQuest Question Relating PLL

I have a design on a DE23-lite board. I use the onboard 50 MHz clock to feed a PLL set to 150 MHz. All registers clock on the PLL. I_clk is the 50 MHz clock. I use the following rule: create_genera...
Timing
sstrell's avatar
sstrell
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4 days ago

This is Agilex 3 so just delete this constraint.  PLL constraints are derived automatically based on your PLL configuration.

jesseopdenbrouw's avatar
jesseopdenbrouw
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4 days ago

Thank you for your answer. But now TimeQuest complains that the input clock has a negative setup slack, even if no flip-flop is clocked on this clock. How do I prevent that?

I_clk    -6.440    -150.246    30 

Greets

Jesse