IOPLL related clock constraints

Agilex 10 is not a current device family (I presume you mean Agilex 3, 5, 7, or 9), but assuming you are using some Agilex device, simply remove derive_pll_clocks and remove that create_generated_clock constraint.  The tool automatically derives PLL output clocks for these devices so no need to add the constraints.  You can even remove create_clock because the IP has you specify the reference clock anyway.

And you said the PLL output pin was iopll_0_outclk0_clk, not iopll_0_outclk0, so that's probably why you're getting the warning.

Sorry, it is Agilex 7 i series FPGA.  

Yes i did configure IOPLL ip block parameters in platform designer. it is parameterized to have 50MHz input clock and one output clock at 300MHz. I will remove both lines (as above in original post) from sdc file and re-run compilation. At the end of SOF generation sometime, quatus pops up Timing analyzer Summary window and I see  summary of violations. How do I get to details per path violations details? 

For Agilex 7 iopll not need manual sdc. The pll will derive clock using auto generated sdc. Below are the statement:

https://www.intel.com/content/www/us/en/docs/programmable/683243/23-3/derive-pll-clocks-derive-pll-clocks.html Note: Only Intel® Arria® 10 and Intel® Cyclone® 10 GX devices support the Derive PLL Clocks (derive_pll_clocks) constraint. For all other supported devices, the Timing Analyzer automatically derives PLL clocks from constraints bound to the related IP.

May I know do you have any further concern on the previous post IOPLL related clock constraints | Altera Community?

Yes, I still need help.

I have removed timing constraints related to IOPLL, I have completed generate programming files step.

in Messages tab I don't see any message indicating any timing violations. I see Green Correct symbols without warning triangle next to Plan , Place , Route, Retime and fitter (Finalize) steps. Does this means the design has no timing violations at all? 

I opened Tasks> Timing analyzer.

The setup summary violations numbers I am seeing has not changed even after I change compilation parameters from balanced to best performance.  I am really questioning, is this the correct and latest set up summary report? and if it is,  how come setup violations remained exactly same despite choosing "best performance" compilation options Vs "balanced" option in previous compilation run? 

In  Timing analyzer console I see 

• warning message  - Timing requirements not met
• info message - Automatically attempting to load the "Design Closure Summary" from the compliation timing reports. To change this behavior, see Timer Analyzer Settings.
• info message - Not able to find relevant "Design Closure Summary" in compilation timing reports. Either the report was not generated for this snapshot or a timing change has occured since compilation.

Once compilation was over I have not changes any timing constraints or any project related files; I have simply clicked on Timing analyzer to review timing reports.

I am bit puzzled about the last info message, what does the message mean? does this mean that latest run has no violations and its showing me old timing summary results?

if it is correctly showing timing violations from latest run, how come setup violations remained exactly same despite choosing "best performance" compilation options Vs "balanced" option in previous compilation run?

I am attaching  setup report here.

I see most of the violation paths are from RAM block - to AVMM interconnect internal buffer.  I need help removing these violations. The "custom_mem_bridge_2port_0"  is dual ported memory ip wrapped into some logic which adds fanout as it provides copy of AVMM signals from mentoring purpose only,  there is no combination logic here. just additional fanouts to S1 and S2 ports goint into DFF inputs and DFF output are used to get copy of AVMM activities for monitoring purpose.

how do i do that ?