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UserID4331231's avatar
UserID4331231
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

IOPLL related clock constraints

Hello Every one  I am struggling with creating clock constraint and need help. I have agilix 10 FPGA design at project level top module I have input "iopll_clk_clk". this input is mapped to clo...
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Timing
UserID4331231's avatar
UserID4331231
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

how do i do that ?

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    1 month ago

    May I know you're using port a and b? For example: altera_syncram_component.outdata_reg_b  = "UNREGISTERED" -> altera_syncram_component.outdata_reg_b  = "CLOCK0"

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    1 month ago

    Any further update on the previous suggestion?