Occasional Contributor
Occasional ContributorSorry, it is Agilex 7 i series FPGA.
Yes i did configure IOPLL ip block parameters in platform designer. it is parameterized to have 50MHz input clock and one output clock at 300MHz. I will remove both lines (as above in original post) from sdc file and re-run compilation. At the end of SOF generation sometime, quatus pops up Timing analyzer Summary window and I see summary of violations. How do I get to details per path violations details?
Super ContributorI'm not sure if you are talking about in the Quartus Compilation Report or in the Timing Analyzer, but you would need to open the Timing Analyzer and generate detailed slack/path reports for failing paths. Start by creating summary reports (setup, hold, recovery, removal) and then right-click failing clock domain and generated detailed reports from there.
