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UserID4331231
Occasional Contributor
Occasional ContributorIOPLL related clock constraints
Hello Every one I am struggling with creating clock constraint and need help. I have agilix 10 FPGA design at project level top module I have input "iopll_clk_clk". this input is mapped to clo...
ShengN_altera
Super Contributor
Super ContributorFor Agilex 7 iopll not need manual sdc. The pll will derive clock using auto generated sdc. Below are the statement:
https://www.intel.com/content/www/us/en/docs/programmable/683243/23-3/derive-pll-clocks-derive-pll-clocks.html Note: Only Intel® Arria® 10 and Intel® Cyclone® 10 GX devices support the Derive PLL Clocks (derive_pll_clocks) constraint. For all other supported devices, the Timing Analyzer automatically derives PLL clocks from constraints bound to the related IP.
