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UserID4331231
Occasional Contributor
Occasional ContributorIOPLL related clock constraints
Hello Every one I am struggling with creating clock constraint and need help. I have agilix 10 FPGA design at project level top module I have input "iopll_clk_clk". this input is mapped to clo...
UserID4331231Occasional Contributor
Occasional Contributorhow do i do that ?
ShengN_altera
Super Contributor
Super ContributorAny further update on the previous suggestion?
