module "custom_mem_bridge_2port_0" definition includes instantiation for dual ported memory as following.
altera_syncram altera_syncram_component (
.address_a (address),
.address_b (address2),
.byteena_a (byteenable),
.byteena_b (byteenable2),
.clock0 (clk),
.clocken0 (ram_clocken0),
.data_a (writedata),
.data_b (writedata2),
.q_a (q_a),
.q_b (q_b),
.rden_a (read),
.rden_b (read2),
.wren_a (wren_a),
.wren_b (wren_b),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address2_a (1'b1),
.address2_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccencbypass (1'b0),
.eccencparity (8'b0),
.eccstatus (),
.sclr (1'b0)
);
defparam
altera_syncram_component.intended_device_family = "Agilex 7",
altera_syncram_component.lpm_type = "altera_syncram",
altera_syncram_component.operation_mode = "BIDIR_DUAL_PORT",
altera_syncram_component.ram_block_type = "AUTO",
altera_syncram_component.byte_size = 8,
altera_syncram_component.numwords_a = 1024,
altera_syncram_component.numwords_b = 1024,
altera_syncram_component.width_a = 64,
altera_syncram_component.width_b = 64,
altera_syncram_component.widthad_a = 10,
altera_syncram_component.widthad_b = 10,
altera_syncram_component.width_byteena_a = 8,
altera_syncram_component.width_byteena_b = 8,
altera_syncram_component.address_reg_b = "CLOCK0",
altera_syncram_component.byteena_reg_b = "CLOCK0",
altera_syncram_component.indata_reg_b = "CLOCK0",
altera_syncram_component.outdata_reg_a = "UNREGISTERED",
altera_syncram_component.outdata_aclr_a = "NONE",
altera_syncram_component.outdata_sclr_a = "NONE",
altera_syncram_component.outdata_reg_b = "UNREGISTERED",
altera_syncram_component.outdata_aclr_b = "NONE",
altera_syncram_component.outdata_sclr_b = "NONE",
altera_syncram_component.clock_enable_input_a = "NORMAL",
altera_syncram_component.clock_enable_output_a = "BYPASS",
altera_syncram_component.clock_enable_input_b = "NORMAL",
altera_syncram_component.clock_enable_output_b = "BYPASS",
altera_syncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altera_syncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altera_syncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altera_syncram_component.init_file = INIT_FILE,
altera_syncram_component.init_file_layout = "Port_A";
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