IOPLL related clock constraints

I am attaching  setup report here.

I see most of the violation paths are from RAM block - to AVMM interconnect internal buffer.  I need help removing these violations. The "custom_mem_bridge_2port_0"  is dual ported memory ip wrapped into some logic which adds fanout as it provides copy of AVMM signals from mentoring purpose only,  there is no combination logic here. just additional fanouts to S1 and S2 ports goint into DFF inputs and DFF output are used to get copy of AVMM activities for monitoring purpose.