IOPLL related clock constraints

Agilex 10 is not a current device family (I presume you mean Agilex 3, 5, 7, or 9), but assuming you are using some Agilex device, simply remove derive_pll_clocks and remove that create_generated_clock constraint.  The tool automatically derives PLL output clocks for these devices so no need to add the constraints.  You can even remove create_clock because the IP has you specify the reference clock anyway.

And you said the PLL output pin was iopll_0_outclk0_clk, not iopll_0_outclk0, so that's probably why you're getting the warning.