Realistic values for set_max_skew

I have a design with asynchronous input and output bus signals.

For the input bus signals I do not care how much time it takes from the Input Ports to the first register. For the output signals I also do not care how much time it takes from the last register to the output ports. The only thing that I really care about is, the skew of the bus signals.

I have created a very simple dummy design and added sdc design constraints.

module top(
      input clk,      
		input [1:0] input_bus,
		output reg [1:0] output_bus
);

reg [1:0] register;

always @(posedge clk) begin
   register <= input_bus;
   output_bus <= register;
end
endmodule

create_clock  -name clk -period 20 [get_ports clk]

set_max_skew -from [get_ports {input_bus[*]}] 0.5
set_max_skew -to [get_ports {output_bus[*]}] 0.5

Timing Analyzer fails.

I do not have a lot of experience with SDC constraints and bus timing. My feelfing is, that 0.5ns bus skew is not unrealistic.

Is my expectation wrong, or am I doing something wrong?