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SimonT's avatar
SimonT
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1 month ago

Realistic values for set_max_skew

I have a design with asynchronous input and output bus signals. For the input bus signals I do not care how much time it takes from the Input Ports to the first register. For the output signals I al...
Timing
sstrell's avatar
sstrell
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1 month ago

What are your set_input_delay and set_output_delay constraints?

SimonT's avatar
SimonT
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1 month ago

I do not have any set_input_dealy and set_output_delay constraints.

The hardware on input and output side is running on a completly independent clock. I do not know what their frequency and phase offset to my clock is.

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    1 month ago

    Then it sounds like you should just false path the I/O.  I don't know if set_max_skew still matches skews on cut paths, but it's worth it to try.