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memory infer
in my project that base agilex7 fpga, I need to use bit mask memory. the bit mask memory rtl behavior as follow. as quartus only support byte mask memory, so I think quartus tool should use logic(ALM registers) implementation instead of M20K. However, the fitter technology map shows that the following rtl behaviors is mapping to the M20k, that cause rtl behavior is inconsistent with fitter netlist. is this quartus eda bug? always @(posedge clk) begin if (ram_wra) data[ram_addra] <= (data[ram_addra] ＆ ~ram_bwma) | (wrp_dina ＆ ram_bwma); end always @(posedge clk) begin if (ram_rdb) wrp_doutb <= data[addrb]; end
Request: Questa Intel FPGA Starter Edition License for Quartus Prime 25.1 (Windows 11)
Hello, I would like to request a Questa Intel FPGA Starter Edition license for my Windows 11 environment. ■ Target Tool - Questa Intel FPGA Starter Edition - Version: 25.1 Standard Edition (bundled with Quartus Prime 25.1) ■ Environment - OS: Windows 11 (Ryzen laptop) - Quartus Prime 25.1 Standard Edition installed - WSL2 installed - No floating license server (local node-locked license required) ■ HOSTID (MAC Address) My machine uses a Realtek Ethernet adapter that remains “enabled” even when the cable is disconnected. Therefore, Questa detects this Ethernet NIC as the primary physical adapter. HOSTID (Ethernet MAC): **16-09-01-1E-94-24** ■ Additional Notes - Wi-Fi is also available, but Questa always selects the Ethernet NIC first. - I confirmed the MAC address using: - `getmac /v /fo list` - `ipconfig /all` - Please generate a node-locked license file (questa_lic.dat) for this HOSTID. Thank you very much for your support.
Timing analysis - long combinational path
Hi, Running Timing Analyzer I get violations due to long combinational paths. Looking at the path in the technology map viewer, it looks like this leftmost block = registerbank holding a configurable value used by the other two modules center/rightmost block = two identical modules using the register-value I can see the long path, but I do not understand why it is implemented like this. Why is the register-value routed through dec_filter:15 to dec_filter:9, and not getting the value directly from the register-bank-module to the left? Is there anything I can do to force a different implementation?
Error(23098) when using IPM_IOPLL on Agliex 7
I am trying to use the IPM_IOPLL in my project on the Intel Agilex 7 FPGA I-Series Transceiver Development Kit (6x F-Tile) but whenever i use it i get the following error: Error(23098): One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: pio_0_2 Error(12274): A critical error occurred while the periphery placement was committed to the atom netlist. The atom netlist is now invalid and the Fitter must be restarted. Info(20273): Intermediate fitter snapshots will not be committed because ENABLE_INTERMEDIATE_SNAPSHOTS QSF assignment is disabled during compilation. Info(20274): Successfully committed planned database. Error: ERROR: An error occurred during automatic periphery placement Error: Quartus Prime Fitter was unsuccessful. 3 errors, 0 warnings Error: Peak virtual memory: 9478 megabytes Error: Processing ended: Tue Feb 24 11:20:55 2026 Error: Elapsed time: 00:01:22 Error: System process ID: 177973 Error(21794): Quartus Prime Full Compilation was unsuccessful. 5 errors, 109 warnings When i use an IOPLL generate from platform designer the project compiles successfully. The code for the IPM_IOPLL is below: inst_mac_iopll : IPM_IOPLL generic map( REFERENCE_CLOCK_FREQUENCY => "100.0 MHz", N_CNT => 1, M_CNT => 10, C0_CNT => 8, C1_CNT => 16, C2_CNT => 32, OPERATION_MODE => "direct", PLL_SIM_MODEL => "Agilex 7 (I-Series)" ) port map( refclk => clk, -- 100MHz input reset => g_rst_d1, outclk0 => i_mac_clk, -- 125MHz output outclk1 => mac_half_clk, -- 62.5MHz output outclk2 => i_ipb_clk, -- 31.25MHz output locked => i_locked ); I am not sure what is causing this error. I am using Quartus Prime Pro 24.3.1 with the DK-SI-AGI040FES board. ThanksQuartus Prim Pro: "Fatal Error: Segment Violation, Access Violation"
Hi, I am working with Quartus Prime Pro 24.1. Unfortunately, I have encountered several issues when compiling my project on different machines and operating systems. While the project compiles and builds the bitstream without any problems on Windows Server 10, I receive a fatal error on Windows 11 and Ubuntu 24 for the same design, at the "support-logic Generation" phase. All machines are relatively powerful and equipped with more than 32 GB of RAM. I have also disabled parallel compilation, but the error still occurs. Additionally, I tested Quartus 24.3.1 and observed the same behavior. Error on Ubuntu24 machine: Error on Win11 machine: Does it have to do with our JESD float license or the JESD IP itself? I'm asking because it seems that we have this issue only with projects that include Altera JESD IP. I would appreciate it if you could help me resolve this issue. Best, SAH
