Featured Content
Forum Widgets
Recent Discussions
Compilation Error (138001) Write permission
Hi, I'm taking a course in FPGA design and is using Quartus Prime Lite 16.1 (Free) and constantly run into permission errors. The latest one is during compilation. Error (138001): Cannot write to directory C:/nnn/AlteraPrj/pipemultQP16_1/Schematic/incremental_db, which is required for storing incremental compilation results. I simply can't find where and how the permission is denied. I've added as much permission as I can in the security-tab in the folder option. Best Regards/ Anna-KarinSolved85Views0likes6Commentsfanout issue
now I develop a project with agilext7 FPGA, the sysclk is 416MHz. the project has still WNS=-500ps TNS=-5000ns violation. from the fitter duplication summary report below, we can see that the most of number of duplicates is 4, how can we improve the number of duplicates to further to reduce fanout and congestion? quartus provides the GLOBAL_SIGNAL_PROMOTION_FANOUT_THRESHOLD setting, which the default is 50. In my project many signal fanout exceed 50, but I doesn't think the signals are being routed global network. so for non-global high fanout signals, what should I do?manually duplicating many high-fanout nets in the RTL is not practical.18Views0likes3CommentsQuesta-sim waveform- How to export to CSV?
I am using Questasim for doing waveform debug. I want to dump current waveform as CSV to apply some analytics on it. When I go to FIle > Export option "waveform" option is greyed out and is not available. I see "Image" option which I dont want; and "VCD" option is also greyed out. please help me on how can i export waveforms I see into CSV format.87Views0likes2CommentsLicencing error for Questa - Altera FPGA Starter Edition 2025.2 (Quartus Prime Pro 25.1std)
Hello, I have the following error window show up after trying to launch Questa. I have downloaded the license, and created a system variable as shown in the other picture. I also tryed following solutions in similar isues discused here, but to no help. I have downloaded this wersion: Intel® Quartus® Prime Lite Edition Design Software Version 25.1 for Windows using the full installer Intel® Quartus® Prime Lite Edition Installer (SFX)87Views0likes1Commentretiming issue
we develop a project with agilex7 fpga and using quartus pro 25.3 version. now we fix timing by analyze the retiming report. we see the following retiming restriction: But the register GEN_REG_INUT.R_DATA[0][0] is directly driven by quartus hyper register, and it has no power up value and no sync reset. the retiming critical path as follow: -------------------------------------------+ ; Critical Chain Details ; +--------------------------+-------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Info ; Register ; Register ID ; Element ; +--------------------------+-------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Power-up Restriction ; ALM Register ; #1 ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0] ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]|q ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~LAB_RE_X221_Y195_N0_I99 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~R1_X221_Y195_N0_I10 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~C4_X220_Y191_N0_I11 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~LOCAL_INTERCONNECT_X220_Y191_N0_I26 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~BLOCK_INPUT_MUX_PASSTHROUGH_X220_Y191_N0_I35 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~LAB_RE_X220_Y191_N0_I39 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn|dataf ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn|combout ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~cw_la_lab/lab_lut6outt[4] ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_LAB_RE_X220_Y191_N0_I138 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C1_X220_Y190_N0_I17 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R1_X220_Y190_N0_I16 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X208_Y190_N0_I2 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X196_Y190_N0_I2 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X195_Y182_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X195_Y174_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X184_Y174_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X172_Y174_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X160_Y174_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X148_Y174_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X136_Y174_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X135_Y166_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X135_Y158_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X135_Y150_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X135_Y142_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X135_Y134_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X124_Y134_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X123_Y126_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X123_Y118_N0_I0 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R0_X123_Y118_N0_I2 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R2_X124_Y118_N0_I15 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R1_X126_Y118_N0_I31 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C1_X126_Y118_N0_I30 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C1_X126_Y119_N0_I30 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_LOCAL_INTERCONNECT_X126_Y120_N0_I61 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_BLOCK_INPUT_MUX_PASSTHROUGH_X126_Y120_N0_I80 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_LAB_RE_X126_Y120_N0_I82 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg|x_pe_pkg_pkt_pack|pack_data_padding_cross~xtophalf/xale2/xcw_ml_le_regctrl/xcw_la_le_regctrl_reg/sclr_out ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg|x_pe_pkg_pkt_pack|x_pack_data_shifter|bcnt[4]|sclr ; Long Path (Critical) ; ALM Register ; #2 ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg|x_pe_pkg_pkt_pack|x_pack_data_shifter|bcnt[4] ; why quartus report the retiming restriction?6Views0likes0CommentsQuartus/Signaltap complains about wrong version
Hello, we are using Quartus prime V24.1.0 for a rather large project. We have various signaltap files stored within git for analysis. Now, from time to time, it happens that quartus throws the following warning/assertion. Obviously, this assertion can be suppressedwith ENABLE_VHDL_STATIC_ASSERTIONS OFF, and everything is working. However this is no soulution as we want to have ENABLE_VHDL_STATIC_ASSERTIONS ON Error (22148): VHDL error at sld_ela_control.vhd(1263): Failure: "The design file sld_ela_control.vhd is released with Q uartus Prime software Version 24.1.0. It is not compatible with the parent entity. If you generated the parent entity us ing the Signal Tap megawizard, then you must update the parent entity using the megawizard in the current release.": exi ting elaboration File: c:/intelfpga_pro/24.1/quartus/libraries/megafunctions/sld_ela_control.vhd Line: 1263 If I remove the signaltap(file) entirely, and readd it, everything works. However, this is very annoying and time consuming. Q1. Why is this assertion triggered in the first place? We do not use any other versions. Q2. How do I "update the parent entity using the megawizard"? I'm unable to find an "update" option. To me deleting signaltap and re-creating it is not an update.... Thanks, Michael329Views0likes26CommentsAgilex3 dcio parsing issue with RSU
Dear support, I am facing with the following issue: Environment: Quartus prime pro 26.1.0 build 110 (03/26/2026) on windows 11 Target board: Agilex3C evaluation kit (non-hps) Cosigned SDM + Authentication enabled Quartus pfg config file attached (manual.pfg.txt) I can successfully program the flash (the rbf helper signed) via Quartus programmer so the generated jic image is there. When I power-cycle the board and check in configuration debugger the RSU status, I get the following picture: attached rsu_dcio_issue.png I tried to generate the boot.rbf: from sof with -o rsu_boot=ON without injecting sdm without signing the rbf from sof with -o rsu_boot=ON with injecting a signed sdm, with signing the rbf (and basically all the combination with/without signing) In all cases I get back this same issue. QSF file also attached. I validated if I can load from configuration debugger the 1) Factory image (entered base address) --> OK 2) P1 image --> OK 3) P2 image --> OK so it looks like the error is either in the tables or in the decision firmware image itself. The decision firmware.rbf image I signed with permission 0x6, the agilex3.zip with permission 0x1 Today I basically iterated through all the possible way and it still fails. If anyone has any idea where to debug it further (online help again not helping too much), please let me know. Since the issue happening at commands those were in the normal and security guideline and where there are not so much parameters I believe it is either: 1) qsf issue, i am missing some assignment or have false setting --> but which one?? 2) quartus sw issue One last thing: Permission for signing SDM was 0x1 Permission for signing BOOT_INFO / FACTORY_IMAGE / User partitions were 0x6 quartus_sign did not allow me to sign BOOT_INFO with 0x1 permission Signing chains: root0 -> 2x QKY: firmware signing key (0x1) + design signing key (0x6) Update: Is this related to the following entry?! Error(22650): File <filename>.jic is corrupted. DCIO/Main section data information is not found | Altera Community - 351710 Update2: After disabling in the .pfg file the factory fallback: <partition reserved="1" fixed_s_addr="1" s_addr="0x00000000" factory_fallback="0" e_addr="0x0020FFFF" fixed_e_addr="1" id="BOOT_INFO" size="0"/> the issue did not happen anymore --> confirming the issue in 351710 still exists with Quartus 26.1 Thank you for your help in advance! Kind regards, PeterSolved102Views0likes5CommentsQuartus 26.1: quartus_asm triggers quartus_pfg despite disabled generation flags
Product: Quartus Prime Pro Edition Version: 26.1.0 Build 110 (03/26/2026) Component: Assembler (quartus_asm) / Programming File Generator (quartus_pfg) Environment: Linux Summary Running quartus_asm with programming file generation explicitly disabled still triggers an internal call to quartus_pfg. This secondary step fails non-deterministically, even when no inputs or environment variables change between runs. Expected Behavior When invoking: quartus_asm ... --set=GENERATE_PROGRAMMING_FILES=OFF --set=GENERATE_RBF_FILE=OFF quartus_pfg should not be invoked at all, or it should be strictly disabled / skipped internally Actual Behavior quartus_asm always invokes quartus_pfg, even with generation disabled. This then leads to quartus_pfg unpredictably succeeding or failing. See attached log file. This leads to inconsistent results across identical runs. Outcomes observed across runs: The attached log file shows exemplary the different outcome of successive runs with no changes in between. The order of these results are interchangeable as observed. 1. Success Quartus Prime Programming File Generator was successful. 0 errors 2. Corruption error Error (19192): File ..._hps_auto.sof is corrupted 3. Segmentation fault *** Fatal Error: Segment Violation ... Reproduction Run repeatedly without changing anything: quartus_asm <proj> --read_settings_files=on --write_settings_files=off -c <rev> --set=GENERATE_PROGRAMMING_FILES=OFF --set=GENERATE_RBF_FILE=OFF Impact Breaks reproducibility guarantees Causes intermittent CI failures Forces workarounds (retry logic, ignoring exit codes, etc.) Undermines trust in assembler output stage Suggested Fixes / Questions Why is quartus_pfg invoked when: GENERATE_PROGRAMMING_FILES=OFF GENERATE_RBF_FILE=OFF? Can this behavior be: disabled completely, or controlled via a strict flag? Is there a known issue with: HPS-related SOF post-processing Workarounds (partial) Re-running the same command sometimes succeeds Running quartus_pfg separately succeeds Ignoring exit codes is unsafe due to real corruption cases Conclusion quartus_asm appears to implicitly depend on quartus_pfg even when disabled, and that dependency is unstable. This behavior is first observed in Quarts 26.1. In 25.3 quartus_asm does not implicitly call quartus_pfg. At minimum, this should be documented; ideally, the invocation should be conditional or removable.47Views0likes5Comments