Introducing the Altera Community AI Responder — Beta
Altera is introducing the AI Responder, an assistant built into the Altera Community to help provide faster, context-aware guidance for Altera product questions. It uses relevant public Altera documentation and Knowledge Database content, with coverage continuing to expand. The AI Responder may provide source references and can hand off complex or out-of-scope questions to an Altera subject-matter expert. As a beta feature, responses may contain errors or omissions, so please review the sources and verify technical guidance against official Altera documentation before implementation. If the response does not fully address your question, add more context and tag ai_responder to continue the discussion. We welcome your feedback as we improve the Community experience.
Possible Quartus 24.1 bug?
Here is the code: interface myif #( parameter int W = 1 )(); typedef struct packed { logic [W-1:0] x; } MYSTRUCT; MYSTRUCT s; modport src ( output s ); modport dst ( input s ); endinterface module top; myif #( .w( 5 ) ) test_if(); test test_module ( .foo( test_if ) ); endmodule module test ( myif.dst foo ); typedef foo.MYSTRUCT MYSTRUCT_COPY; $info( "%0d %0d", $bits( foo.MYSTRUCT ), $bits( MYSTRUCT_COPY ) ); MYSTRUCT_COPY q; assign q = foo.s; endmodule Surprisingly, the info message will print "5 1" instead of "5 5". And for the assign Quartus will complain that it had to crop the 5 bit wide foo.s to match the 1 bit wide q. When processing the typedef, Quartus uses the interface definition's default W value instead of the actual value of the actual interface port. I believe that, according to the standard, that is not the expected behaviour.Typedef inheritance in nested modules
Sorry for the formatting, but for some reason proper switching between paragraph and preformatted does not work. I have an interface, which contains a structure, which, in turn, contains a parametrised width vector: interface myif #( parameter int W = 1 )(); typedef struct packed { logic one; logic [W-1:0] many; } MYSTRUCT; MYSTRUCT x; modport src ( output x ); modport dst ( input x ); endinterface Now, there is a module which gets this interface. It needs to work with the data defined in the interface, so it needs to extract the structure definition (note that everything here is simplified to absolute bare bones). Easy enough: module my_outer_module ( myif.dst dest ); // Extract the typedef from the port typedef dest.MYSTRUCT MYSTRUCT; ... // other stuff ... // here will be a nested module, described below ... endmodule So far so good, the entity that instantiates my_outer_module also instantiates the interface, with whatever W parameter value it deems necessary and my_outer_module will use the correct MYSTRUCT definition, even though W has not been passed to it . Furthermore, if my_outer_module contains a nested module, as per SystemVerilog rules, it can refer to all types and parameters in the enclosing scope, so it will also be able to use MYSTRUCT without further ado. And, indeed, this works: module my_nested_module ( ... some signals in and out ... ); MYSTRUCT some_variable; ... endmodule However, if the typedef is used in the module port definition, Quartus Pro 24.1 spits the dummy: module my_nested_module ( input MYSTRUCT going_in, output MYSTRUCT coming_out ); assign coming_out = going_in; endmodule Quartus complains about undefined net type for both going_in and coming_out. How come? Help with this particular issue would be appreciated. I know that there are other ways of passing types to modules. There are reasons why I try to solve the problem this particular way and not through packages or macro trickery or anything else. I am looking for an explanation why Quartus reports an error on, I believe, perfectly valid SV source. I know that the simulator is a very different animal, but it accepts the code without a pip, and it works as expected. Thanks in advance. Interesting addendum: using old (non-ANSI) style module declaration makes Quartus happy. Which makes the whole thing more intriguing. This is accepted: module my_nested_module ( going_in, coming_out ); input MYSTRUCT going_in; output MYSTRUCT coming_out; assign coming_out = going_in; endmodule So Quartus clearly understands the concept of using a structure defined in the enclosing scope as the type of a port, but refuses to remember how to do it while processing an ANSI style module header.Issue with MIPI CSI2 Encrypted IP File During Project Integration
Hi, I am working on a project where I have integrated two separate projects into a single top-level design. Project A includes the MIPI CSI2 IP and other related components. Project B contains the logic to process the output data generated by the MIPI CSI2 IP. When I compile both projects individually, they complete successfully without any errors. However, after instantiating both projects together in a single top-level wrapper, I encounter a compilation error originating from the generated encrypted file of the MIPI CSI2 IP. I have attached the error snapshot for your reference. Could you please help identify the possible cause of this issue? Is there any known limitation or configuration requirement when integrating the MIPI CSI2 IP with additional logic in the same top-level design? Thanks.
How to create a Packaged Subsystem in TCL
I am hoping to create a script which will automatically package the IP I am working on as a packaged subsystem. So far, I have automated the creation of an IP directory which describes a new component using a _hw.tcl file and the various source files. I believe the next step is to take this component, instantiate it in a Platform Designer system, and create a Packaged Subsystem using it. I am also hoping that I can parameterise and hide/modify ports of the packaged subsystem, like I can with the _hw.tcl component description. I am encountering a problem; I am running the following command: qsys-script --script=create_packaged_subsystem.tcl --new-quartus-project=my_project_name However, the script fails for the following reason: Error: invalid command name "set_package_property" Here is the script itself (more or less a copy-and-paste from the GUI): package require -exact qsys 26.1 set_package_property NAME "packagename" set_package_property DISPLAY_NAME "PackageName" set_package_property VERSION "1.0" set_package_property GROUP "GroupName" set_package_property DESCRIPTION "A descripton." set_package_property ELABORATION_CALLBACK elaboration_callback set_package_property EXTRACTION_CALLBACK extraction_callback add_fileset synth_fileset QUARTUS_SYNTH fileset_callback "Quartus Synthesis Fileset" add_fileset sim_verilog_fileset SIM_VERILOG fileset_callback "Simulation Verilog Fileset" proc elaboration_callback {} { enable_all_instances } proc extraction_callback {} { extract_modules } proc fileset_callback { output_name } { generate_all_instances } Any help would be hugely appreciated, on this issue and on my general workflow. Also if it is possible to encrypt packaged subsystems or components using Quartus I'd be keen to know. Thanks!
FIR IP configured for Interpolation
Why does my Altera FIR IP, configured for interpolation by 80, produce the expected outputs when I provide 3 input samples, but fail to produce the expected behavior when I provide 10 input samples? In this case, the FIR IP keeps tready asserted high, but only generates 4 valid outputs. What could be causing this behavior? I am simulating this in Quartus Prime Lite Edition.
