FIR IP configured for Interpolation
Why does my Altera FIR IP, configured for interpolation by 80, produce the expected outputs when I provide 3 input samples, but fail to produce the expected behavior when I provide 10 input samples? In this case, the FIR IP keeps tready asserted high, but only generates 4 valid outputs. What could be causing this behavior? I am simulating this in Quartus Prime Lite Edition.
How to create a Packaged Subsystem in TCL
I am hoping to create a script which will automatically package the IP I am working on as a packaged subsystem. So far, I have automated the creation of an IP directory which describes a new component using a _hw.tcl file and the various source files. I believe the next step is to take this component, instantiate it in a Platform Designer system, and create a Packaged Subsystem using it. I am also hoping that I can parameterise and hide/modify ports of the packaged subsystem, like I can with the _hw.tcl component description. I am encountering a problem; I am running the following command: qsys-script --script=create_packaged_subsystem.tcl --new-quartus-project=my_project_name However, the script fails for the following reason: Error: invalid command name "set_package_property" Here is the script itself (more or less a copy-and-paste from the GUI): package require -exact qsys 26.1 set_package_property NAME "packagename" set_package_property DISPLAY_NAME "PackageName" set_package_property VERSION "1.0" set_package_property GROUP "GroupName" set_package_property DESCRIPTION "A descripton." set_package_property ELABORATION_CALLBACK elaboration_callback set_package_property EXTRACTION_CALLBACK extraction_callback add_fileset synth_fileset QUARTUS_SYNTH fileset_callback "Quartus Synthesis Fileset" add_fileset sim_verilog_fileset SIM_VERILOG fileset_callback "Simulation Verilog Fileset" proc elaboration_callback {} { enable_all_instances } proc extraction_callback {} { extract_modules } proc fileset_callback { output_name } { generate_all_instances } Any help would be hugely appreciated, on this issue and on my general workflow. Also if it is possible to encrypt packaged subsystems or components using Quartus I'd be keen to know. Thanks!
Quartus/Signaltap complains about wrong version
Hello, we are using Quartus prime V24.1.0 for a rather large project. We have various signaltap files stored within git for analysis. Now, from time to time, it happens that quartus throws the following warning/assertion. Obviously, this assertion can be suppressedwith ENABLE_VHDL_STATIC_ASSERTIONS OFF, and everything is working. However this is no soulution as we want to have ENABLE_VHDL_STATIC_ASSERTIONS ON Error (22148): VHDL error at sld_ela_control.vhd(1263): Failure: "The design file sld_ela_control.vhd is released with Q uartus Prime software Version 24.1.0. It is not compatible with the parent entity. If you generated the parent entity us ing the Signal Tap megawizard, then you must update the parent entity using the megawizard in the current release.": exi ting elaboration File: c:/intelfpga_pro/24.1/quartus/libraries/megafunctions/sld_ela_control.vhd Line: 1263 If I remove the signaltap(file) entirely, and readd it, everything works. However, this is very annoying and time consuming. Q1. Why is this assertion triggered in the first place? We do not use any other versions. Q2. How do I "update the parent entity using the megawizard"? I'm unable to find an "update" option. To me deleting signaltap and re-creating it is not an update.... Thanks, MichaelDocumentation of recent low-level and WYSIWYG primitives
Hello, it has been previously stated that Altera doesn't provide documentation of low-level primitives for newer FPGA series, e.g. Cyclone 10 GX or Agilex. See e.g. WYSIWYG documentation | Altera Community - 273853 What if I want to implement e.g. an octal SPI interface utilizing DDR and DQS driven data sampling with calibration? I presume that my IP would use tennm_io_12_lane and tennm_tile_ctrl primitives. They are published in Quartus as interface definition in tennm_components and a .xml parameter list. Can you provide additional information under NDA? Regards Frank
Interfacing Avalon Streaming FIFO IP with GTS Ethernet Hard IP
Hello, I want to integrate the Avalon Streaming Single Clock FIFO IP (AVST FIFO IP) with the GTS Ethernet Hard IP (GTS EHIP) , but the GTS EHIP outputs signals rxstatus_valid and rxstatus_data, that don't interface with the AVST FIFO IP. The AVST FIFO IP is in a custom module in between the GTS EHIP and the rest of the 1x10G Ethernet System Example Design: Agilex 5 FPGA E-Series Modular Development Kit (Link: https://altera-fpga.github.io/rel-25.3/embedded-designs/agilex-5/e-series/modular/ethernet/agx5e-ethernet-10g/ug-agx5e-ethernet-10g/). How should I handle these signals? Can I ignore them? Is there a example reference design that does this? Thank you for the help! IP Blocks: AVST FIFO Parameters:Using Reset Release IP (Agilex, Stratix) without IP catalog via simple instantiation is ok?
Anything against using the reset release IP without going the IP catalog -> Platform Designer way bey simply: -- library clause to make the altera library containing -- the internal implementation of reset release IP visible library altera_s10_user_rst_clkgate_1949; ... entity... ... end entity; architecture ... -- declaring the component for VHDL fitting the internal -- reset release IP (name and port naming have to fit -- for VHDL default binding) component altera_s10_user_rst_clkgate is port ( ninit_done : out std_logic -- ninit_done ); end component altera_s10_user_rst_clkgate; signal nInitDone : std_ulogic; begin -- instantiation of the reset release IP TheResetRelease : component altera_s10_user_rst_clkgate port map ( ninit_done => nInitDone -- ninit_done.reset); -- combine the asynchronous reset signal combinatorially with the -- nInitDone signal in the further code ... end architecture Rtl; This would speed up things and has improved readability also. If it is not ok, please give concrete reasons speaking against this approach.
