dut.p0_hip_status has no associated reset.

Hello Altera 

I am using Quartus Prime Pro 25.1.0 build 129 03/26/2025  SC Pro Edition.

In my Agiliex 7 Design project, I have  Intel R-Tile MCDMA for PCI Express intel_pcie_rtile_mcdma Version 5.3.1 Ip instantiated as "dut". in parameters settings I have enabled to have hip status interface.  

this interface is connected to a custom design QCP file. The QCP uses "app_clk"  and "app_nreset_status" from dut ip as its clk and reset inputs. THey go through clock bridge and reset bridge. Clock and reser outputs from these bridges are used internally in QCP creation 

In platform designer as I connect "dut.p0_hip_status" and "custom_module_pcie_ep_hip_status_in" I get an error as following 

"Error: pcie_ed: Interfaces custom_module_pcie_ep_hip_status_in and dut.p0_hip_status must have matching associated resets, but dut.p0_hip_status has no associated reset."

This Error does not make sense to me, as dut`s hip status interface and my qcp`s status interface ports shows correct clock and reset association in component instantiation tab; and my custom design uses same clock and reset to its clock and reset bridge inputs. 

can you please help me to understand what is this error about and how do i resolve it?