Hi,
VHDL example, inclock 16 MHz, outclock 50 MHz
library ieee;
use ieee.std_logic_1164.all;
entity plltest_min is
port
(
inclk0 : in std_logic := '0';
c0 : out std_logic
);
END plltest_min;
architecture inst of plltest_min is
component altpll
generic
(
bandwidth_type : string;
clk0_divide_by : natural;
clk0_duty_cycle : natural;
clk0_multiply_by : natural;
clk0_phase_shift : string;
inclk0_input_frequency : natural;
operation_mode : string;
pll_type : string;
compensate_clock : string := "CLK0";
self_reset_on_loss_lock : string
);
port
(
inclk : in std_logic_vector (0 downto 0) := (others => '0');
areset : in std_logic := '0';
clk : out std_logic_vector (0 downto 0);
locked : out std_logic
);
end component;
begin
mypll : altpll
generic map (
bandwidth_type => "AUTO",
clk0_divide_by => 16,
clk0_duty_cycle => 50,
clk0_multiply_by => 50,
clk0_phase_shift => "0",
inclk0_input_frequency => 62500, -- 16 MHz
operation_mode => "NORMAL",
pll_type => "AUTO",
self_reset_on_loss_lock => "ON"
)
port map (
inclk(0) => inclk0,
clk(0) => c0
);
end inst;
Verilog example
module vpll_min (
inclk0,
c0);
input inclk0;
output c0;
wire [4:0] clk;
assign c0 = clk[0];
altpll altpll_component (
.areset (1'b0),
.inclk ({1'b0, inclk0}),
.locked (),
.clk (clk));
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 16,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 50,
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 62500,
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
Regards
Frank
Occasional Contributor
