avalon MM generator read issue
I'm using avalon MM BFM to stimuli my slave avalon interface, however, when doing u_avalon_MM_gen.mm_master_bfm_0.set_command_address(addr); u_avalon_MM_gen.mm_master_bfm_0.set_command_byte_enable(4'hF, 0); u_avalon_MM_gen.mm_master_bfm_0.set_command_request(REQ_READ); u_avalon_MM_gen.mm_master_bfm_0.push_command(); @(u_avalon_MM_gen.mm_master_bfm_0.signal_read_response_complete); data = u_avalon_MM_gen.mm_master_bfm_0.get_response_data(0); $display("[%0t] READ Addr=0x%08h Data=0x%08h", $time, addr, data); I'm always getting 0. but i have seeing correct data on avm_readdata, when avm_waitrequest=0 there is no read_data_valid, avm_response=0 Am i doing something wrong or missing a command?
DDR2 license Question
The customer obtained the DDR2 license through the Altera website. Does this IP license have any time limitation or other usage restrictions? When generating the project for the EP4CE75U19I7N device, Quartus only generates project.sof and does not generate project_time_limited.sof.
QPP 26.1 fails to generate PLL IP
Hello, I'm unable to generate a simple PLL IP on a particular Win 11 machine. It works fine on a different Win 11 machine. Below is a partial log that shows the error. Note that I replaced my own user name with <username> below. Info: Starting: Create HDL design files for synthesis Info: qsys-generate C:\Projects\fw_ml_module_local\ip\pll_io.ip --synthesis=VERILOG --output-directory=C:\Projects\fw_ml_module_local\ip\pll_io --family="Agilex 3" --part=A3CY050BB18AI6S Info: pll_io.iopll_0: Able to implement PLL with user settings Info: pll_io: "Transforming system: pll_io" Info: pll_io: "Naming system components in system: pll_io" Info: pll_io: "Processing generation queue" Info: pll_io: "Generating: pll_io" Info: pll_io: "Generating: pll_io_altera_iopll_2110_txusefy" Error: add_fileset_file: No such file C:/altera_pro/26.1/ip/altera/altera_iopll/top/{C:/Users/<username>/AppData/Local/Temp/alt0637_15290807326924327962.dir/0003_iopll_0_gen/altera_falconmesa_ph2_iopll.sdc} while executing "add_fileset_file ${output_name}.sdc SDC_ENTITY PATH $sdc_file {NO_AUTO_INSTANCE_DISCOVERY NO_SDC_PROMOTION READ_DURING_POST_SYN_AND_POST_FIT_TIMING_AN..." (procedure "generate_sdc_related_files" line 560) invoked from within "generate_sdc_related_files $tmpdir $name " (procedure "generate_sdcs_and_mif" line 24) invoked from within "generate_sdcs_and_mif $name" (procedure "generate_synth_falconmesa_ph2" line 12) invoked from within "generate_synth_falconmesa_ph2 $name" (procedure "generate_synth" line 9) invoked from within "generate_synth pll_io_altera_iopll_2110_txusefy" Info: pll_io: Done "pll_io" with 2 modules, 4 files Info: Finished: Create HDL design files for synthesis Info: Generation of C:/Projects/fw_ml_module_local/ip/pll_io.ip (pll_io) took 9192 ms When I run the same PLL generation on a different Win 11 machine, I don't see mention of add_fileset_file in the log. Below are the Generation settings.Fitter Error with Clock Switchover Enabled in Altera PLL (Normal Mode)
Hi everyone, I ran into the following Fitter Error when enabling Clock Switchover on an Altera PLL in Normal mode: Error (14996): The Fitter failed to find a legal placement for all periphery components Info (14987): The following components had the most difficulty being legally placed: Info (175029): fractional PLL altera_pll_blk:u0|altera_pll_blk_0002:altera_pll_blk_inst|altera_pll:altera_pll_i|altera_arriav_pll:arriav_pll|altera_arriav_pll_base:fpll_0|fpll (100%) Error (14986): After placing as many components as possible, the following errors remain: Error (175001): The Fitter cannot place 1 fractional PLL, which is within PLL Intel FPGA IP altera_pll_blk. Info (14596): Information about the failing component(s): Info (175028): The fractional PLL name(s): altera_pll_blk:u0|altera_pll_blk_0002:altera_pll_blk_inst|altera_pll:altera_pll_i|altera_arriav_pll:arriav_pll|altera_arriav_pll_base:fpll_0|fpll Error (16234): No legal location could be found out of 2 considered location(s). Reasons why each location could not be used are summarized below: Error (12349): Fitter was unable to route the far global PLL feedback path for the fractional PLL (2 locations affected) Info (175029): FRACTIONALPLL_X97_Y31_N0 Info (175029): FRACTIONALPLL_X97_Y40_N0 Info (175013): The fractional PLL is constrained to the region (97, 30) to (97, 47) due to related logic Info (175015): The I/O pad CLKIN is constrained to the location PIN_N2 due to: User Location Constraints (PIN_N2) Info (14709): The constrained I/O pad is contained within a pin, which drives this fractional PLL Quartus Info Quartus Prime Standard Edition v25.1 Device: Arria V ( 5AGXBA1D4F27C4 ) PLL IP Settings [ General ] tab PLL Mode: Integer-N PLL Operation Mode: Normal Feedback Clock: Global Clock [ Clock Switchover ] tab Automatic Switchover with Manual Override Pin Assignments CLK50M → PIN_M1 (BANK 5A) — refclk1 ( Secondary clock for Clock Switchover ) CLKIN → PIN_N2 (BANK 5A) — refclk ( Primary clock for Clock Switchover ) Sample Design top_module_a5_lvds_rx_Qstd_ver251NG.qar When I change the PLL mode from Normal to Direct, the Fitter Error disappears and the design compiles successfully. However, in Direct mode, phase compensation is not applied, so I’d prefer to stick with Normal mode. Question: What could be the root cause of this Fitter Error in Normal mode, and how can I resolve it while: ・ Keeping Normal mode ・ Keeping the current pin assignments Any guidance or workaround would be greatly appreciated. Thanks!
Stratix 10 fPLL is cascade source mode doesn't lock
Hello everyone. I use fPLL cascading with Stratix 10 FPGA: fPLL in cascade source mode is connected to fPLL in transceiver mode. In my design reference clock for fPLL in cascade source mode is not stable after power-up and I apply user recalibration to it. But after user recalibration when reference clock is stable, fPLL doesn't set lock signal. After some investigation of the issue, I found that my design works fine with Quartus Pro 21.2 but doesn't work with newer versions like Quartus Pro 23.4/25.1/26.1. Is there any known issue about fPLL is cascade source mode? Any suggestions about how to overcome this issue are welcomed.
AVST FIFO and AVST Demultiplexer IP Simulation Behavior
Hi, I am using Quartus version 25.3. I simulated 2 IP's independently and had questions about their behavior. 1. For the Avalon Streaming (AVST) Demultiplexer IP (figure 1) , is there a reason why the endofpacket (eop) signal remains asserted after the packet leaves the output, when I simulate with packet support (figure 2)? Is this normal? AVST Demultiplexer IP version 19.3.1. 2. For the AVST SC FIFO (Figure 3) , is there a reason the negative edge of output eop is unknown (red) (Figure 4)? Is this normal? AVST SC FIFO version 19.3.2. Thank you for the help! AVST Demultiplexer Parameters: AVST Demultiplexer Waveform: AVST SC FIFO Parameters: AVST SC FIFO Waveform:System ID IP Timestamp Issue
I would like to get compile timestamp using System ID Peripheral IP (ver: 19.1.8) which is connected to NIOS-V IP (26.0.0). I am using Quartus Prime Pro 25.1.1. Using the NIOS program I am able to correctly access and print the System ID parameter that has been configured (0x12345679), but the returned timestamp seems to be wrong (printing: Tue Feb 4 18:03:27 2003, versus today's date). Would you please advise if I am making any mistake in accessing the SysID timestamp, and if there is any other configuration that needs to be done on the IP? Following is my code running on the Nios-V processor and the corresponding printout
Cascaded Avalon Stream Multiplexer in Platform Design does not forward valid data packets
Hello community, I have a DSP system with 32 independent 256-bit output channels using Avalon-ST (or AXI-Stream) on an AGX FPGA. To transfer packetized data to the HPS, I implemented a cascaded Avalon Streaming Multiplexer architecture. The 32 channels are divided into two groups of 16. Each group connects to a 16-to-1 Avalon-ST Multiplexer IP. The outputs of these two multiplexers are then connected to a final 2-to-1 Avalon-ST Multiplexer IP, forming an overall 32-to-1 mux structure. At the output of the final 2-to-1 mux, I also added another 2-to-1 Avalon-ST mux with a selectable input for a data packet emulator. Using the emulator path, I verified that the FPGA-to-HPS data path is functioning correctly. However, after switching from the emulator path to the DSP output path, I only receive packets from channel 0. No packets from the other DSP channels are observed by the HPS. For debugging, I intentionally generated valid packets on non-zero channels. In SignalTap, I observed that channel 28 was asserting valid packet data (valid = 1) while ready = 0. This capture was taken at the input of the second 16-to-1 mux, since channel 28 belongs to the upper 16-channel group. Next, I changed the SignalTap trigger condition to the rising edge of the output valid signal of the second 16-to-1 mux. However, the trigger condition was never met, even after repeated acquisitions. The ready signals throughout the mux stages remain asserted, which suggests there is no downstream backpressure from the FIFO path to HPS. The downstream FIFO status also indicates that it is empty. The confusing part is the following: After enabling channel 0 again, both channel 0 and channel 28 should have had valid packets simultaneously. In this case, packets from channel 0 were forwarded correctly to the HPS. I verified this by reading 8 words from the memory FIFO and reconstructing the original packet; all received packets contained the channel ID corresponding to channel 0. However, after disabling channel 0 again, no new packets were received from any channel, including channel 28. Based on these observations, it appears that the internal round-robin scheduler of the Avalon-ST mux may not be operating correctly. The two 16-to-1 muxes and the final 2-to-1 mux are all configured identically in Platform Designer. Does anyone have suggestions on what could cause this issue, or recommendations on how to further debug the Avalon-ST mux behavior? I noticed an interesting behavior on channel 28 related to the Avalon-ST handshake. The ready signal for channel 28 remains asserted during idle cycles, but it becomes deasserted exactly when valid is asserted. In other words: | Cycle | valid | ready | | ---------- | ----- | ----- | | Idle | 0 | 1 | | Data cycle | 1 | 0 | | Next cycle | 0 | 1 | This differs from channel 0, where both valid and ready are asserted simultaneously, forming a successful Avalon-ST handshake. My DSP source currently only pulses `valid` for one cycle when data is available. Could the Avalon-ST Multiplexer scheduling size setting (Scheduling Size = 2) contribute to this behavior? Specifically, can the mux arbitration latency caused by the scheduling configuration prevent non-zero channels from completing a handshake if valid is only asserted for one cycle? Thank you very much.Why does Fitter show "Dedicated Pin" as "Reference Clock Source by" for downstream PLL in cascade?
Hi everyone, I created a design that connects two PLLs in a simple cascaded configuration. However, I noticed something that seems inconsistent in the Fitter report: In the Resource Section → PLL Usage Summary, the "Reference Clock Sourced by" field for the downstream side PLL shows "Dedicated Pin". This seems unusual because it does not reflect the actual connection (which uses the upstream side PLL’s cascade output). On the other hand, the "PLL Refclk Select" section in the report looks correct and matches the intended cascading setup. Could anyone explain why this discrepancy occurs? Is this normal behavior or a reporting issue in Quartus Prime? Environment: Tool: Quartus Prime Standard Edition version 23.11 Target Device: Cyclone V GX (5CGXFC5F6M11C6) Target IP: "Altera PLL" or "PLL Intel FPGA" Sample Design: Simple_Two_plls_shortest_cascading_refclk_from_clkpin.qar Settings Summary (Only the key parameters are listed.): Upstream side PLL: In [General] tab PLL Mode: Integer-N PLL Operation Mode: Normal Feedback Clock: Global Clock In [Cascading] tab "Create a 'cascade_out' signal to connect with a downstream PLL" : Enabled ( PLL Use As Upstream PLL. → Create cascade_out signal ) In [Settings] tab Bandwidth Preset: Low Downstream side PLL: In [General] tab PLL Mode: Integer-N PLL Operation Mode: Normal Feedback Clock: Global Clock In [Cascading] tab "Create an adjpｌｌin or cclk signal to connect with an upstream PLL" : Enabled ( PLL Use As Downstream PLL → Create adjpll_in or cclk signal ) In [Settings] tab Bandwidth Preset: High Thank you for any insights on this!
Why the Error Response Slave IP cannot work for Agilex 5 SOC FPGA?
I test the GHRD and corresponding linux image on Terasic DE25-Nano board， however, when I access the FPGA peripheral device, like SW, I use md.l 0x20010060 1 command in U-Boot console, it reports the register value; when I use md.l 0x2fffffff 1 (the H2F ummapped address) or md.l 0x4fffffff 1 (the LWH2F ummapped address), the system will hang up, report Please reset the board! then I added a Error Response Slave IP and tested, but it still report the same message, then, I need reboot my system every time. I set the IP as follows: after this, I added two Error Response Slave IPs in the system, one is for H2F, another is for LWH2F: Unfortunately, the problem still remains unsolved.
