Agilex 5: Connecting multiple AXI Masters to DDR without explicit Interconnect IP

Hi all,

I'm developing on the Agilex 5 platform and need two AXI4 masters to access the DDR.

I noticed there isn't a standalone IP similar to Xilinx's axi_interconnect. Is it correct to simply connect two AXI masters directly to the single DDR AXI slave port (as shown below)? Will the interconnect fabric generate the necessary arbitration and routing logic in this case？