Forum Discussion
Occasional ContributorF-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer
Hello Support,
I am using the Agilex 7F Dev Kit with F-Tile configured in Root Port Gen3x4. When I am doing a Configuration Write Type 0 to write the End Point BAR0 with FFFF_FFFFh, the end point send an answer , when I follow this write with a Configuration Read type 0 to read the BAR 0 of the End point I do not receive any answer.
- Is there any configuration which avoid the read data to go through the F-Tile ?
- Is there any problem with my Configuration Read type 0 command
I have attached the STP file as well.
Thank you for help.
Serge
You may need to recheck your design if a given valid is not seen by the IP.
Here is how a F-Tile RP reads another FPGA's VID.
18 Replies
RongY_alteraContributor
Hi Serge,
When I am doing a Configuration Write Type 0 to write the End Point BAR0 with FFFF_FFFFh
>>This doesn't look right. For a BAR test, I think you should use MWr and MRd.
Regards,
Rong
Serge93Hello Rong,
Nice to see you again.
BAR0 in address 10h, is in the Configuration Space not in the Memory Space, so you have to use a Configuration Access. I am using the same access with my Agilex7i-R-Tile board and it is working. So this is very strange it is not working on the Agilex-7F board.
Thanks for help.
Serge- RongY_altera
Thanks for the clarification. I misunderstood your request in the previous message.
From the stp, you were reading addr 0x01000010, not 0x10.
Regards,
Rong
- Serge93
Hello Rong,
When using a Configuration Write or Read Request the address is compose of : Bus Number(7:) & Device Nb(7:0) & Ext_Reg(7:0) & reg Nb(7:0).
So what you see is the Bus Number=01h and Reg Nb=10h.
By the way, I have the same behaviour with the address=00h (Device ID & Vendor ID) in the Configuration Space.
Thanks for help.
Serge
- RongY_altera
The F-Tile is RP so it's type1. The CfgWr0 to EP BAR0 with FFFF_FFFFh is for finding the BAR0 size, right? Once the EP BAR0 is enabled, the RP can read/write to that BAR.
Thus you need to set BDF on RP(type1), and enable BAR0 on EP(type0).
Regards,
Rong
- Serge93
Rong,
Can you translate your last sentence in bus access to the RP IP in order I understand what you mean.
Thank you.
Serge
- Serge93
Rong,
I recall you the bus access sequence I show you is working with R-Tile. This is exactly the same sequence.
So why It is not working with F-Tile ?
Thank you.
Serge- RongY_altera
I think you should trigger tx_st_valid.
Regards,
Rong
