Forum Discussion
Occasional ContributorF-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer
You may need to recheck your design if a given valid is not seen by the IP.
Here is how a F-Tile RP reads another FPGA's VID.
ContributorThe F-Tile is RP so it's type1. The CfgWr0 to EP BAR0 with FFFF_FFFFh is for finding the BAR0 size, right? Once the EP BAR0 is enabled, the RP can read/write to that BAR.
Thus you need to set BDF on RP(type1), and enable BAR0 on EP(type0).
Regards,
Rong
Serge93Rong,
Can you translate your last sentence in bus access to the RP IP in order I understand what you mean.
Thank you.
Serge
- Serge93
Rong,
I recall you the bus access sequence I show you is working with R-Tile. This is exactly the same sequence.
So why It is not working with F-Tile ?
Thank you.
Serge- RongY_altera
I think you should trigger tx_st_valid.
Regards,
Rong
- Serge93
Hello Rong,
When I trig on tx_st_valid, it never trigs.
Do you have a PCIe specialist I can have access ?
Thanks.
Serge
