Agilex-7 AXI MCDMA for PCIe hang
Hi! I'm working with AGIB023R18A1E1VC device and having issues with AXI Multichanned DMA IP for PCIe. Since I require a PCIe bridge, I configured the IP in MCDMA+BAS+BAM mode (PCIe Gen 4, 512-bit), generated an example design, and integrated the subsystem into my project. Although I do not use MCDMA, I rely heavily on the BAS and BAM functionality. The issue I’m seeing is that writing more than 448 bytes to the BAS causes the host to hang and subsequently reset. Notably, between the write transaction and the host reset, the FPGA internal logic is still able to write to the BAS, indicating no hang on the AXI bus. There are no issues with read transactions. We observe this issue not with only one card. At first we run into it in Q25.1 but still have it in Q25.3.1 If you need some captures from the signal tap or any additional details I may provide them. Thank you in advance! Mikhail.
Cyclone 10GX PCIe / Raspberry Pi
Hi, We have a PCIe controller using the Cyclone 10Gx with the PCIe hard IP. It works when connected to a Windows system but it isn't getting detected when connected on a Raspberry Pi 5 or CM5 system. On the Pi, i see that the LTSSM transitions from Detect.Active to Polling.Active to Polling.Compliance to link down. I think this suggests that the Pi isn't detecting any device on the other end. I tried isolating the power on sequencing by hooking up an external power supply to the PCIe card, but it didn't help. Any guidance would be much appreciated. Thanks!
agilex 7 Platform Designer PIO addr width
I am using the PIO example design of the P-Tile AVST PCIe IP on Intel Agilex 7. The original design maps a 16KB RAM to BAR0. Since my design requires a larger address space, I modified the PCIe IP's BAR configuration to increase BAR0 size to 2MB. However, I soon discovered that in the "PIO Design Example for PCI Express Gen4," the module converting AVST to AVMM only supports a 16KB address space after conversion. I then replaced it with the "PCIe PIO" IP core, but found that it can only access a 1MB region. What should I do?Agilex-7 MSI-X missing om AXI MCDMA for PCIe
Hi! We are using AGIB023R18A1E1VC device and AXI MCDMA for PCIe IP core. We set it to MCDMA+BAS+BAM mode as we want to use MSI-X interrupts. Our driver register for example 2 MSI-X interrupts in Linux with no issues, after that FPGA logic sends request to user_msix interface and observes handshake. But then we see no interrupt happening in host, and interrupts counter stays at zero value. In lspci we see that MSI-X capability exists and the number of MSI-X vectors is not zero. Capabilities: [b0] MSI-X: Enable+ Count=53 Masked- Vector table: BAR=0 offset=00100000 PBA: BAR=0 offset=00180000 We use Q25.3.1. Could you please help us with understanding what may be wrong and why we don't see interrupts in our host system? Thank you in advance. Mikhail.
Agilex 7 R-Tile PIPE Direct Mode: Raw Rx Data Misalignment - Is Soft Word Alignment Needed?
Hello, I am designing a custom PCIe Logical PHY using Agilex 7 R-Tile in PIPE Direct Mode. My goal is to implement the PCS/MAC layer in soft logic (FPGA fabric). I have established a link with the Host, but I am unable to detect the COM symbol (K28.5). Instead, I observe the following two repeating patterns on the 10-bit RxData bus via Signal Tap: Observed Raw Data (Repeating 10-bit Hex values): Pattern A (RD-): 0x3E5, 0x142, 0x147, 0x267, 0x30E, 0x236, 0x156, 0x155, 0x155, ... Pattern B (RD+): 0x01D, 0x2BD, 0x2B8, 0x198, 0x0F1, 0x1C9, 0x151, 0x155, 0x155, ... My Analysis: The trailing 0x155 matches D10.2 (TS1 Link/Lane ID), which is symmetric (0101010101), so it looks correct even if bit-reversed. The header 0x3E5 (Pattern A) and 0x01D (Pattern B) do not match K28.5 directly. However, if I apply Bit Reversal and a 3-bit Shift to 0x3E5, it perfectly matches the K28.5 comma pattern. This strongly suggests the data is valid but is coming in as Raw, Bit-Reversed, and Misaligned bits. My Questions: In PIPE Direct Mode, is it standard behavior for the R-Tile Hard IP to bypass Word Alignment and output raw, unaligned data? Does this mean the user is strictly responsible for implementing Bit Reversal and a Soft Word Aligner (Bit Slip / Barrel Shifter) in the FPGA fabric to achieve Symbol Lock? Is there any IP parameter or configuration to enable Hard Word Alignment while keeping the PIPE Direct interface? I would appreciate any confirmation or advice from those experienced with R-Tile PIPE Direct mode. Thank you.agilex 7 Platform Designer PIO 2x8
I used the Platform Designer PIO 2x8 example to build my own setup, but when I run lspci on the computer, I can only see one device pcie1, and cannot see pcie0. My hardware connections should be fine - I have two clock signals, and it works with the pcie pio x16 example. Where might I have configured something incorrectly? The settings for pcie1 are basically the same as pci0. I'll post the parts that are different. What have I missed or what have I configured incorrectly?
Behavior of 10 GX Avalon-MM Interface for PCI Express* IP Core when byteenable=16'h0000
Hi, we are using an Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* IP Core. During our tests we noticed some illegal PCIe packages generated presumable due to a wrong data length. We could tackle down the problem to the following basic setup: avalon_mm_master => 128 bit bus => PCIe-Core When we send the following sequence (two words), we get an illegal/unexpected PCIe transfers/behavior: burstcount = 2, address = address_a, data = some_data, byteenable=16'h0000 burstcount = 1, address = address_a+16, data=some_data, byteenable=16'hFFFF When we only send the second word everything works fine. This sequence originally comes from a qsys autogenerated 256=>128 width change in the interconnect somewhere upstream in our project. My question is: Do we miss something here? Does the IP-Core not allow for a first word to be completely disabled? If so, is there any (automatic) way to tell qsys / the interconnect to discard a leading all_bytes_disabled word? 5.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals Best regards, Michael
