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MichaelL's avatar
MichaelL
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2 months ago

Behavior of 10 GX Avalon-MM Interface for PCI Express* IP Core when byteenable=16'h0000

Hi,

we are using an Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* IP Core.

During our tests we noticed some illegal PCIe packages generated presumable due to a wrong data length. We could tackle down the problem to the following basic setup:

avalon_mm_master => 128 bit bus => PCIe-Core

When we send the following sequence (two words), we get an illegal/unexpected PCIe transfers/behavior:

  1. burstcount = 2, address = address_a, data = some_data, byteenable=16'h0000
  2. burstcount = 1, address = address_a+16, data=some_data, byteenable=16'hFFFF

When we only send the second word everything works fine. This sequence originally comes from a qsys autogenerated 256=>128 width change in the interconnect somewhere upstream in our project.

My question is: Do we miss something here? Does the IP-Core not allow for a first word to be completely disabled? If so, is there any (automatic) way to tell qsys / the interconnect to discard a leading all_bytes_disabled word? 5.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals

Best regards,

Michael 

Pcie
Transceiver

6 Replies

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    1 month ago

    Hi MichaelL

    Thank you for reaching out.
    We sincerely apologize for the delayed response—due to an issue with our queue, we missed your post until now.

    If you still need assistance, please let us know. We apologize for any inconvenience this may have caused and appreciate your understanding.

    Thanks.
    Best Regards,
    Ven 

  • MichaelL's avatar
    MichaelL
    Icon for New Contributor rankNew Contributor
    1 month ago

    Hi VenT_Altera​,

    although we currently have a workaround, it would be very helpful to know, if empty words are allowed or not. 

    Best Regards,

    Michael

    • VenT_Altera's avatar
      VenT_Altera
      Icon for Frequent Contributor rankFrequent Contributor
      1 month ago

      Hi MichaelL 

      I understand your concern, and I apologize for the delayed response. I hope this answers your question.

      Does the IP-Core not allow for a first word to be completely disabled? 
      No. Based on the user guide description for txs_byteenable_i[<w> -1:0], the first and final data phases of a burst can have other valid values. For the 128-bit interface,  the following patterns are legal for the first and final word:
      ○ 16'hF000
      ○ 16'h0F00
      ○ 16'h00F0
      ○ 16'h000F
      ○ 16'hFF00
      ○ 16'h0FF0
      ○ 16'h00FF
      ○ 16'hFFF0
      ○ 16'h0FFF
      ○ 16'hFFFF 

      Therefore, 16'h0000 is not a legal pattern for the first word.

      Thanks.
      Best Regards,
      Ven 

      • MichaelL's avatar
        MichaelL
        Icon for New Contributor rankNew Contributor
        1 month ago

        Oh, thanks for clarifying

        However, that's very unfortunate as the illegale transfer is generated by the qsys's avalon-interconnect-structure.