Forum Discussion
New ContributorCan't generate F-Tile Ethernet Hard IP Design Example
When I try to generate an example design for the F-Tile Ethernet Hard IP or even the F-Tile Low Latency 100G Ethernet IP, the generating step gets stuck in a loop and will stay that way until I manually stop it in Task Manager. Has anyone else encountered this issue?
6 Replies
paveetirrasrie_AlteraFrequent Contributor
Hello,
May I know which Quartus version you're working with? Do the issue still persist?
Regards,
Pavee
dc3I upgraded to 25.3.1 and now I get this error.
- paveetirrasrie_Altera
Hello,
Form the screenshot you've provided, the design has error. You won't be able to generate the design with error.
Please select the valid Device Initialization Clock and continue with generation.
Regards,
Pavee
- dc3
After retrying again, the generation step loops like before. Is there any way I could get a pre-made example design to download instead?
