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nalingam's avatar
nalingam
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1 month ago

Altera Agilex PCIe core

Hi Altera Team, 

We have developed a user reset controller based on the "Cold Reset Entry and Exit Sequence" described in the "GTS AXI Streaming IP for PCI Express User Guide for Agilex® 5 and Agilex® 3 FPGAs and SoCs". 

Currently, our implementation is stalled at Step 2 of the reset sequence. Our user reset logic is waiting for the PCIe IP to assert the p<n>_initiate_warmrst_req signal; however, this signal is never asserted during simulation. 

Our current PCIe configuration is as follows: 

* PCIe x 4lanes
* AXI Streaming interface: 128-bit
* PLD clock: 200 MHz
* Reference clock: 100 MHz
* System PLL configured as required 

Could you please advise on the possible reasons why p<n>_initiate_warmrst_req may not be asserting? Additionally, are there any configuration settings or reset timing requirements that must be satisfied before the PCIe IP generates this signal?

Pcie

5 Replies

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    1 month ago

    Hi nalingam 

    Thanks for reaching out to us.  
    Please allow me sometime to investigate your issue, I will get back to you with an update shortly.  

    Thanks. 
    Best Regards, 
    Ven 

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    29 days ago

    Hi nalingam, 

     

    Apologies for the late reply. 

    You can check the following: 

    • p<n>_initiate_warmrst_req is an output from the IP to the user reset controller. For the PERST#-triggered cold-reset path, cold reset is initiated by deassertion of p<n>_pin_perst_n_i (PERST# released: low → high). The IP then asserts p<n>_initiate_warmrst_req, and your controller should respond with p<n>_subsystem_rst_req. 
    • For a user-initiated cold reset, start by asserting p<n>_subsystem_rst_req. In that flow, initiate_warmrst_req is not the trigger and is not required. 
    • Before PERST# deassertion in simulation, ensure ninit_done is 0 (device configured). 
    • Compare your reset controller and PERST# timing against the design example generated in Quartus Prime for this IP. Refer to the following Design Example user guide for the steps to generate a Design Example: https://docs.altera.com/r/docs/817713/25.3/gts-axi-streaming-ip-for-pci-express-design-example-user-guide/about-the-gts-axi-streaming-ip-for-pci-express-design-example

     

    Thanks. 

    Best Regards, 

    Ven

    • VenT_Altera's avatar
      VenT_Altera
      Icon for Frequent Contributor rankFrequent Contributor
      24 days ago

      Hi nalingam,


      May I know if you have any updates on this forum? 


      Thanks.

      Best Regards, 

      Ven

      • nalingam's avatar
        nalingam
        Icon for New Contributor rankNew Contributor
        24 days ago

        Hi Ven,

        Thank you for your response. Our team already working with Altera APS team to solve this issue. Please close this case for now.