Altera Agilex PCIe core

Hi Altera Team, 

We have developed a user reset controller based on the "Cold Reset Entry and Exit Sequence" described in the "GTS AXI Streaming IP for PCI Express User Guide for Agilex® 5 and Agilex® 3 FPGAs and SoCs". 

Currently, our implementation is stalled at Step 2 of the reset sequence. Our user reset logic is waiting for the PCIe IP to assert the p<n>_initiate_warmrst_req signal; however, this signal is never asserted during simulation. 

Our current PCIe configuration is as follows: 

* PCIe x 4lanes
* AXI Streaming interface: 128-bit
* PLD clock: 200 MHz
* Reference clock: 100 MHz
* System PLL configured as required 

Could you please advise on the possible reasons why p<n>_initiate_warmrst_req may not be asserting? Additionally, are there any configuration settings or reset timing requirements that must be satisfied before the PCIe IP generates this signal?