How to handle tx_st_ready for Cyclone V PCIe

I'm using a Cyclone V GT with PCIe core using Gen 1 Avalon-ST 64-bit endpoint interface. Everything works pretty well including sending and receiving data, DMA transfers etc. But so far I've ignored the situation where tx_st_ready is deasserted during a packet transmission. Time to deal with it, but the docs are a bit confusing.

For example, the following implies I have some sort of control over the readyLatency, but I see nothing in the core generator to set that. How to I know what the readyLatency is?

And what to they mean the "typical case"? 

In the above, are they saying I should register them? I see nothing in the core generator to say if they should be registered or not. 

They give a timing diagram below which is a bit confusing.