Agilex7 M PCIe MCDMA: debug toolkit attachment

Hi,
I'd need advice on how to connect Quartus PCIe Debug Toolkit to MCDMA IP in Agilex7 M. Since I'm failing to find or generate a complete example design, I'm not sure if I have to manually instantiate a JTAG Avalon master as a debug interface, or can I assume Quartus to generate the debug connection under the hood. I have read "Multi Channel DMA IP for PCI Express* Design Example User Guide" and "Multi Channel DMA IP for PCI Express* User Guide".

Creating an example design of MCDMA IP configured with Debug Toolkit enabled fails on my Windows 11 machine with Quartus 25.3. Originally there was an access right problem occurring when the generation script tried to delete some temporary files in Temp under Appdata. I tried it also on workmate's PC, with the same result. After changing some user access control setting the script started failing at a later stage of processing, where it tries to read some test bench files even though I had TB files generation unchecked in parameter editor. However after the failed generation, a sample design exists. It defines all Debug Toolkit related MCDMA ports as virtual pins in .QSF. I thought this might be intentional, Quartus possibly detecting them and magically creating the missing attachment. I have this method under test, Quartus flow not yet complete.

Manually using a JTAG-Avalon master component to build the debug link did pass Quartus flow, but timing between xcvr_reconfig_clk and slow_clock of PCIe MCDMA component fails as the clock relation between these two 100 MHz clocks is ~ 90 ns for some reason. I took xcvr_reconfig_clk from an internal IOPLL as the design is not an EVKIT one with suitable input clocks.

Thank in advance if anyone can provide some insight.. should the example design contain more than virtual pins defined on xcvr_reconfig*, dummy_user_avmm_rst, p0_dtk_hip_reconfig_clk ? (Documented port  p0_hip_reconfig does not seem to appear in my MCDMA instance.)

BR
Ju-Ti