need for Agilex 5 utilization&performance support in Altera IP ?

Good questions, Glen — let me address each point directly.

DSP Builder as a wrapper / workflow question

No, you don't need to use DSP Builder as a top-level wrapper for all DSP IP work. The relationship is more nuanced:

• The FIR II IP supports DSP Builder — use the DSP Builder flow if you want to create a DSP Builder model that includes an IP variation; use IP Catalog if you want to create an IP variation you can instantiate manually in your design. FIR II IP Core: User Guide
• The Unified FFT IPs use the same high-level synthesis technology as DSP Builder for Altera FPGAs Unified FFT IPs User Guide , but to include the IP in a design, you generate the IP in the Quartus Prime software Unified FFT IPs User Guide directly — DSP Builder is not required as an outer wrapper.
• The high-level synthesis technology allows you to generate an IP that specifically targets the selected device family, speed grade, and frequency. Unified FFT IPs User Guide

FIR II IP — missing Agilex 5 performance/utilization numbers

You're right that the performance tables in the FIR II IP User Guide currently only cover Arria V, Cyclone V, and Stratix V devices — there are no Agilex 5 entries in the documentation available to me. This is a valid documentation gap. The FIR II IP optimizes hardware utilization by using time-division multiplexing (TDM), where the TDM factor (or folding factor) is the ratio of the clock rate to the sample rate FIR II IP Core: User Guide — so the actual resource count is heavily parameterization-dependent anyway, which makes a single table harder to generalize. Running compilation in Quartus Prime Pro on your target Agilex 5 device and speed grade is the reliable path to accurate numbers for your specific configuration.

Unified FFT IP — Agilex 5 support but no utilization/performance table

The Unified FFT IPs support Agilex 5 devices, along with Agilex 7, Arria 10, Cyclone 10 GX, and Stratix 10 devices. Unified FFT IPs User Guide You are correct that no pre-generated utilization or fmax table exists in the guide for Agilex 5. Your instinct about the workflow is also correct: if you update the Quartus Prime software, you must regenerate the IP Unified FFT IPs User Guide , and the numbers you see pre-P&R are estimates — final fmax and utilization are only confirmed after full synthesis and place-and-route. The IP generation step in Quartus gives you a starting point, but Fitter reports after a full compile are what you should design against for timing closure decisions.

Legacy FFT IP Core — Agilex 5 support status

The older FFT IP Core is a separate product from the Unified FFT IPs. Altera recommends using the Unified FFT IPs and not the FFT IP Core unless the global enable-based flow control in Unified FFT IPs is not suitable for your requirements Unified FFT IPs User Guide , or you require an in-place or memory-based architecture for low-rate applications. Unified FFT IPs User Guide Regarding Agilex 5 and the FFT IP: the migration guide for Cyclone V to Agilex 5 lists the FFT IP as enabled in Quartus Prime Pro Edition Version 24.3, with the IP reuse action guideline being to upgrade the IP core to the latest version. Cyclone® V to Agilex™ 5 Device Migration Guide So if you're migrating an existing design using the older core, upgrading to the latest version is the path forward, but for new designs targeting Agilex 5, the Unified FFT IPs are the recommended choice.

The bottom line on the documentation gaps: your feedback is valid. For Agilex 5-specific FIR II and Unified FFT performance/utilization figures, generating the IP for your specific parameterization (transform size, data width, device, speed grade) and running a full Quartus compile is currently the only reliable method to get device-specific numbers.

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Thank you very much.