Forum Discussion
GTS SDI II IP System PLL Frequency Issue in Quartus Prime Pro Edition 26.1.1
Hello,
I would like to confirm an issue regarding the System PLL frequency of the GTS SDI II IP.
According to the KDB article “Synthesis Critical Violation: IPC-40026 - System clock frequency mismatch,” there is a known issue in Quartus Prime Pro Edition 25.3 where IPC-40026 occurs when the System PLL frequency is set to a value other than 700 MHz. The article also states that this issue is planned to be fixed in a future release.
https://community.altera.com/kb/knowledge-base/synthesis-critical-violation-ipc-40026---system-clock-frequency-mismatch/353567
However, we have confirmed that the same issue still occurs in Quartus Prime Pro Edition 26.1.1.
If the version in which this issue is planned to be fixed has been determined, could you please let us know?
Best regards,
1 Reply
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Thank you very much.