Agilex3/5 GTS Hard Ethernet IP 10G example design pin loc and io std wanted
Where can I find any public available dev kit design example for the Agilex3 or Agilex which can implement the GTS Eth HIP as generated by Quartus Pro v25.3 and successfully build a sof file? A set of pin locations and IO standard settings for the AXE5 Eagle would be optimal, but any other dev kit would be helpful. According to the "GTS Ethernet Hard IP User Guide: Agilex 3 FPGAs and SoCs" (848477) page 29 under "Target Development Kit Tab" is says: "Target development kit option specifies the target development kit used to generate the project. Ensure the pin assignments in the .qsf file are appropriate." But it seems like this will only set the BOARD parameter in the resulting qsf, e.g. when using the Premium Development Kit it results in the following addtion to the qsf file: set_global_assignment -name BOARD "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1" which results in no location or IO standard settings in the qsf and I/O Assignment Warnings in the fitter report after the build: +-----------------------------------------------------------------------------------------------------------------------+ ; I/O Assignment Warnings ; +-----------------------+-----------------------------------------------------------------------------------------------+ ; Pin Name ; Reason ; +-----------------------+-----------------------------------------------------------------------------------------------+ ; o_tx_serial_data[0] ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; ; o_tx_serial_data_n[0] ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; ; qsfp_lowpwr ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; ; qsfp_rstn ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; ; i_reconfig_clk ; Missing I/O standard ; ; i_rx_serial_data_n[0] ; Missing I/O standard ; ; i_rx_serial_data[0] ; Missing I/O standard ; ; i_clk_ref_p ; Missing I/O standard ; ; o_tx_serial_data[0] ; Missing location assignment ; ; o_tx_serial_data_n[0] ; Missing location assignment ; ; qsfp_lowpwr ; Missing location assignment ; ; qsfp_rstn ; Missing location assignment ; ; i_reconfig_clk ; Missing location assignment ; ; i_rx_serial_data_n[0] ; Missing location assignment ; ; i_rx_serial_data[0] ; Missing location assignment ; ; i_clk_ref_p ; Missing location assignment ; ; i_refclk2pll_p ; Missing location assignment ; +-----------------------+-----------------------------------------------------------------------------------------------+ Whenever I try to assign these myself I get errors like Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IPFLUXTOP_UXTOP_WRAP(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number. Error (175001): The Fitter cannot place 1 IPFLUXTOP_UXTOP_WRAP, which is within GTS Ethernet Hard IP ex_10G_intel_eth_gts_1000_6dyx4dq. or this or other type of layout or clocking type constraint errors: Error (11216): Output port "O_SYSPLL_C0" of "SM_HSSI_PLL_WRAP" cannot connect to PLD port "CLK" of "FF" for node "kr_dut|intel_eth_anlt_gts_0|ip_inst|sip_inst|u_intel_eth_anlt_gts_csr_top|u__intel_eth_anlt_gts_csr_avmm_arb|o_avmm_rdata[0]". It would be nice if I could obtain a set of correct and working pin assignment which actually results in a working sof file so I can try to understand what the actual constraints are. Is there a dev kit as described which the pin assignments are generated or provided or could anybody please provide a set of pin assignments for the above signals for a dev kit? Cheers!
Cyclone 10GX PCIe / Raspberry Pi
Hi, We have a PCIe controller using the Cyclone 10Gx with the PCIe hard IP. It works when connected to a Windows system but it isn't getting detected when connected on a Raspberry Pi 5 or CM5 system. On the Pi, i see that the LTSSM transitions from Detect.Active to Polling.Active to Polling.Compliance to link down. I think this suggests that the Pi isn't detecting any device on the other end. I tried isolating the power on sequencing by hooking up an external power supply to the PCIe card, but it didn't help. Any guidance would be much appreciated. Thanks!Transceiver data corruption
I am trying to externally loopback a simple data-stream using the GTS on the Agilex 5, over an external QSFP loopback module. The GTS is configured as followed: External clock chip: Outputs 156.25 MHz clock verified using an oscilloscope. System PLL: Outputs 125 MHz to the GTS. GTS: Basic PMA Direct System PLL freq: 125 MHz PMA speed: 1250 Mbps PMA width: 10 TX/RX PLL/CDR: 156.25 MHz TX/RX core interface FIFO: single width TX/RX clock: System PLL clock /1 The RTL used to transfer data over TX: module top( input CPU_RESET_n, input REFCLK, output gts_o_tx_serial_data, output gts_o_tx_serial_data_n, input gts_i_rx_serial_data, input gts_i_rx_serial_data_n ); // gts logic gts_pma_cu_clk_i; logic gts_tx_reset, gts_rx_reset; logic gts_tx_reset_ack, gts_rx_reset_ack; logic gts_tx_ready, gts_rx_ready; logic tx_coreclkin, rx_coreclkin; (* noprune *) logic gts_tx_clkout, gts_rx_clkout; logic gts_rs_grant_i; logic gts_rc_rs_req_o; (* noprune *) logic gts_tx_pll_locked /* synthesis keep */; (* noprune *) logic gts_rx_is_lockedtodata /* synthesis keep */; (* noprune *) logic gts_rx_is_lockedtoref /* synthesis keep */; logic o_refclk2core; (* noprune *) logic [79:0] gts_i_tx_parallel_data /* synthesis keep */; (* noprune *) logic [79:0] gts_o_rx_parallel_data /* synthesis keep */; assign gts_pma_cu_clk_i = srcss_bank1_pma_cu_clk_o; assign tx_coreclkin = gts_tx_clkout; assign rx_coreclkin = gts_rx_clkout; assign gts_rs_grant_i = srcss_bank1_rs_grant_o; // reset sequencer signals logic srcss_bank1_rs_grant_o; logic srcss_bank1_rs_priority; logic srcss_bank1_rc_rs_req; logic srcss_bank1_pma_cu_clk_o; assign srcss_bank1_rs_priority = '0; assign srcss_bank1_rc_rs_req = gts_rc_rs_req_o; // system pll signals logic gts_systempll_refclk_rdy; assign gts_systempll_refclk_rdy = 1'b1; gts_top u0 ( // gts .gts_top_clock_bridge_rx_in_clk_clk (QSFP_REFCLK_p), .gts_top_clock_bridge_tx_in_clk_clk (QSFP_REFCLK_p), .intel_directphy_gts_0_i_pma_cu_clk_clk (gts_pma_cu_clk_i), .intel_directphy_gts_0_i_tx_reset_tx_reset (gts_tx_reset), .intel_directphy_gts_0_i_rx_reset_rx_reset (gts_rx_reset), .intel_directphy_gts_0_o_tx_reset_ack_tx_reset_ack (gts_tx_reset_ack), .intel_directphy_gts_0_o_rx_reset_ack_rx_reset_ack (gts_rx_reset_ack), .intel_directphy_gts_0_o_tx_ready_tx_ready (gts_tx_ready), .intel_directphy_gts_0_o_rx_ready_rx_ready (gts_rx_ready), .intel_directphy_gts_0_i_tx_coreclkin_clk (tx_coreclkin), .intel_directphy_gts_0_i_rx_coreclkin_clk (rx_coreclkin), .intel_directphy_gts_0_o_tx_clkout_clk (gts_tx_clkout), .intel_directphy_gts_0_o_rx_clkout_clk (gts_rx_clkout), .intel_directphy_gts_0_i_src_rs_grant_src_rs_grant (gts_rs_grant_i), .intel_directphy_gts_0_o_src_rs_req_src_rs_req (gts_rc_rs_req_o), .intel_directphy_gts_0_o_tx_serial_data_o_tx_serial_data (gts_o_tx_serial_data), .intel_directphy_gts_0_o_tx_serial_data_n_o_tx_serial_data_n (gts_o_tx_serial_data_n), .intel_directphy_gts_0_i_rx_serial_data_i_rx_serial_data (gts_i_rx_serial_data), .intel_directphy_gts_0_i_rx_serial_data_n_i_rx_serial_data_n (gts_i_rx_serial_data_n), .intel_directphy_gts_0_o_tx_pll_locked_o_tx_pll_locked (gts_tx_pll_locked), .intel_directphy_gts_0_o_rx_is_lockedtodata_o_rx_is_lockedtodata (gts_rx_is_lockedtodata), .intel_directphy_gts_0_o_rx_is_lockedtoref_o_rx_is_lockedtoref (gts_rx_is_lockedtoref), .intel_directphy_gts_0_o_refclk2core_o_refclk2core (o_refclk2core), .intel_directphy_gts_0_i_tx_parallel_data_i_tx_parallel_data (gts_i_tx_parallel_data), .intel_directphy_gts_0_o_rx_parallel_data_o_rx_parallel_data (gts_o_rx_parallel_data), // reset sequencer signals .intel_srcss_gts_0_o_src_rs_grant_src_rs_grant (srcss_bank1_rs_grant_o), .intel_srcss_gts_0_i_src_rs_priority_src_rs_priority (srcss_bank1_rs_priority), .intel_srcss_gts_0_i_src_rs_req_src_rs_req (srcss_bank1_rc_rs_req), .intel_srcss_gts_0_o_pma_cu_clk_clk (srcss_bank1_pma_cu_clk_o), // system pll signals .intel_systemclk_gts_0_i_refclk_rdy_data (gts_systempll_refclk_rdy) ); // syncronise reset logic gts_tx_system_reset; altera_reset_synchronizer #( .ASYNC_RESET (1), .DEPTH (2) ) gts_tx_rst_sync ( .reset_in (~CPU_RESET_n), .clk (gts_tx_clkout), .reset_out (gts_tx_system_reset) ); // generate test data stream logic [7:0] counter; logic [7:0] test_stream; always_ff @(posedge gts_tx_clkout or posedge gts_tx_system_reset) begin if (gts_tx_system_reset) begin counter <= 8'b0; test_stream <= 8'b0; end else begin counter <= counter + 1; case (counter) 8'd0: test_stream <= 8'h3C; 8'd1: test_stream <= 8'h7F; 8'd2: test_stream <= 8'h11; 8'd3: test_stream <= 8'h07; default: test_stream <= 8'h00; endcase end end // detect and transform idle data, and mark control symbols logic [7:0] idle_data_transform; logic control_symbol_detect; always_comb begin idle_data_transform = (test_stream == 8'h00) ? 8'hBC : test_stream; control_symbol_detect = (idle_data_transform == 8'h1C) || (idle_data_transform == 8'h3C) || (idle_data_transform == 8'h5C) || (idle_data_transform == 8'h7C) || (idle_data_transform == 8'h9C) || (idle_data_transform == 8'hBC) || (idle_data_transform == 8'hDC) || (idle_data_transform == 8'hFC) || (idle_data_transform == 8'hF7) || (idle_data_transform == 8'hFB) || (idle_data_transform == 8'hFD) || (idle_data_transform == 8'hFE); end // pipline combinational logic to ensure timings are met logic [7:0] idle_data_transform_r; logic control_symbol_detect_r; always_ff @ (posedge gts_tx_clkout or posedge gts_tx_system_reset) begin if(gts_tx_system_reset) begin idle_data_transform_r <= 8'b0; control_symbol_detect_r <= 1'b0; end else begin idle_data_transform_r <= idle_data_transform; control_symbol_detect_r <= control_symbol_detect; end end // --- 8b/10b Encoding --- // https://libsv.readthedocs.io/en/latest/encoder_8b10b.html logic [9:0] encoded_out; logic code_error; encoder_tx encoder_inst ( .i_clk (gts_tx_clkout), .i_reset_n (~gts_tx_system_reset), .i_en (1'b1), .i_8b (idle_data_transform_r), .i_ctrl (control_symbol_detect_r), .o_10b (encoded_out), .o_code_err (code_error) ); // pipeline encoded outputs to ensure timing is met logic [9:0] encoded_out_r; always_ff @(posedge gts_tx_clkout or posedge gts_tx_system_reset) begin if (gts_tx_system_reset) encoded_out_r <= 10'b0; else encoded_out_r <= encoded_out; end // send data over TX logic data_path_rdy_tx; always_ff @(posedge gts_tx_clkout or posedge gts_tx_system_reset) begin if (gts_tx_system_reset) begin gts_i_tx_parallel_data <= 80'b0; data_path_rdy_tx <= 0; end else begin data_path_rdy_tx <= gts_tx_ready && gts_tx_pll_locked; case (data_path_rdy_tx) 1: gts_i_tx_parallel_data <= {1'b1, 39'b0, 1'b0, 1'b1, 28'b0, encoded_out_r}; 0: gts_i_tx_parallel_data <= 80'b0; endcase end end endmodule This RTL passes timing standalone, but when signal tap is used, it does produce warnings. In SignalTap I take the following measurments: Instance TX: data: gts_i_tx_parallel_data[79:0] clock domain: gts_tx_clkout Instance RX: data: gts_i_rx_parallel_data[79:0] clock domain: gts_rx_clkout The issue I am seeing is intermitted failures upon bitstream-re-configure: On the TX side, after the encoder has encoded, the TX data reads as folowed: (EXPECTED): ... 283, 17C, 283, 17C, 183, 335, 0B1, 347, 283, 17C, 283, 17C, ... This is the expected pattern on the RX side (post-framing) However, in my experiments so far, I have found that it only sometimes works: Here are the framing results after 5 different re-flashes: (FAILURE): ... 283, 17C, 283, 17C, 383, 135, 0B1, 347, 083, 37C, 283, 17C, ... (FAILURE): ... 283, 17C, 283, 17C, 383, 135, 0B1, 347, 083, 37C, 283, 17C, ... (FAILURE): ... 283, 17C, 283, 17D, 183, 335, 0B1, 346, 283, 17C, 283, 17C, ... (SUCCESS): ... 283, 17C, 283, 17C, 183, 335, 0B1, 347, 283, 17C, 283, 17C, ... (FAILURE): ... 283, 17C, 283, 175, 1B1, 307, 083, 37C, 283, 17C, 283, 17C, ... If anyone has any idea of what else to try, it would be much appreciated!
IO Standard for GTS Transceiver REFCLK
Hi, We use on the Agilex 5 and 3 Transceivers with AC coupling. Agilex 5 requires CML, HCSL in Agilex 5 datasheet. However, Agilex 5 Premium kit uses LVDS Clock for some Transceiver REFCLK. Is it possible to use LVDS as REFCLK for XCVRs when we use with AC Coupling ?Altera Agilex3 vs Xilinx Zynq & AD9363
Hi I would like to know if using an Altera Agilex 3/5 for an RF design makes sense. Xilinx has many materials that make an engineer's job easier. Are there also materials for Agilex 3/5? See Xilinx (3 projects only, but there is much more...): -> https://www.youtube.com/watch?v=HDEegX9IoUg -> https://github.com/hz12opensource/libresdr -> https://wiki.analog.com/resources/eval/user-guides/adrv936x_rfsom We are evaluating to build something like this: -> https://wiki.analog.com/resources/eval/user-guides/adrv936x_rfsom Thanks!
Behavior of 10 GX Avalon-MM Interface for PCI Express* IP Core when byteenable=16'h0000
Hi, we are using an Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* IP Core. During our tests we noticed some illegal PCIe packages generated presumable due to a wrong data length. We could tackle down the problem to the following basic setup: avalon_mm_master => 128 bit bus => PCIe-Core When we send the following sequence (two words), we get an illegal/unexpected PCIe transfers/behavior: burstcount = 2, address = address_a, data = some_data, byteenable=16'h0000 burstcount = 1, address = address_a+16, data=some_data, byteenable=16'hFFFF When we only send the second word everything works fine. This sequence originally comes from a qsys autogenerated 256=>128 width change in the interconnect somewhere upstream in our project. My question is: Do we miss something here? Does the IP-Core not allow for a first word to be completely disabled? If so, is there any (automatic) way to tell qsys / the interconnect to discard a leading all_bytes_disabled word? 5.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals Best regards, Michael
