Agilex 7 I F-Tile Direct PHY: example TB doesn't work
Hello community, I'm unable to run an example design for F-Tile on Agilex 7 I-Series device. I've tried following: 1. generate an example design using platform designer, 2. open the generated project using quartus and click Support-Logic Generation, 3. Tools -> Generate Simulator Setup Script for IP, select output directory "sim" inside the generated project, 4. Using QuestaSim go into freshly generated "sim/mentor" folder and put: do run_msim_setup.tcl set TOP_LEVEL_NAME top_tst elab_debug add waves for u0, u1 instances, 5. run 2 ms (100 us will do it too) 6. See that the rx_ready doesn't go up (but tx_ready does). Used tools: Quartus: 26.1 pro QuestaSim: 2023.4, 2025.3, 2026.1 OS: Debian 13, Windows 11. What could lead to such behavior? Is there something could be done differently? Any ideas? Best regards.
About the System PLL in Agilex 5
Regarding the System PLL in Agilex 5, the reference clock input can be supplied not only from the dedicated transceiver input pins but also from HVIO pins. However, when assigning the pins, the following Critical Warning occurs. Critical Warning(24190): User has specified a QSF location assignment to drive XPIN_GTS_CLK[0] using PIN_BK19. The PIN_BK19 is on HVIO bank and is not optimal for HSSI PLL refclk usage. Try to use the HSSI native local/global refclk IO instead. Additionally, this HVIO location assignment could cause the Reset Sequencer to be placed into a invalid shoreline. To avoid this, besides the PLL refclk, you must also specify location assignment for the UX native refclk. Is the operation acceptable, and what are the jitter characteristics? Also, are there specific ways to address the Critical Warning?
Agilex 7 F-Tile 200G hard IP de-feature clarification
There is a point in the Agilex 7 known issues list in UG-683584 for some silicon revisions The F-Tile Ethernet 200G Hard IP block is de-featured and cannot beused in production devices with OPNs that have no suffix (blank) or "B" suffix Does this mean that 200G "bonded" hard-IP is not supported in those older OPNs, such as 200GE-4 / 200GE-8 ? Or does it mean that all parts of 200G hard IP is de-featured? For example would FEC/PCS/MAC still work in 10/25/50GE-1 configurations?
Stratix 10 fPLL is cascade source mode doesn't lock
Hello everyone. I use fPLL cascading with Stratix 10 FPGA: fPLL in cascade source mode is connected to fPLL in transceiver mode. In my design reference clock for fPLL in cascade source mode is not stable after power-up and I apply user recalibration to it. But after user recalibration when reference clock is stable, fPLL doesn't set lock signal. After some investigation of the issue, I found that my design works fine with Quartus Pro 21.2 but doesn't work with newer versions like Quartus Pro 23.4/25.1/26.1. Is there any known issue about fPLL is cascade source mode? Any suggestions about how to overcome this issue are welcomed.
Tranceiver Enhanced PCS Basic mode questions
Hello Guys, We used Arria GX and Straitx IV GX devices before, now we switch to use Cyclone 10 GX FPGA. I have several simple questions about XCVR's control port/signal. Why I can't see rx_control and tx_control ports when I make "Enable simplified data interface" ON? In basic or custom mode, 1 bit control signal corresponding 8-bit parallel data bits. I read XCVR user guide, it seems that only LSB 2-bits of the control bus will be used to recognize/indicate data word or control word?
GTS Transceiver Simulation Model Encrypted file - unable to decrypt with Cadence Xcelium
Hi everyone, I am working on integrating the generated simulation models of the Agilex-5 GTS PMA/FEC Direct PHY IP with our main IP. I have encountered an issue where an encrypted file within the models cannot be decrypted by the Cadence Xcelium Simulator. The file is located at: <ip>/n_channel_superset_2100/sim/intelfpga/intel_src_flow_ctrl.sv I have tested this with Cadence Xcelium versions 19.x, 20.x, and 22.x, but the decryption error persists across all versions. We are currently using Quartus Pro Edition 2026.1.0 with an evaluation license. Could you please provide guidance on how to resolve this decryption issue? Thanks, ArunInterfacing Avalon Streaming FIFO IP with GTS Ethernet Hard IP (Agilex 5, quartus v25.3)
Hello, I posted this question before on the Quartus Prime Forum but saw this forum and thought maybe this would be a better place to post it. Sorry if this is considered spam and not allowed: I want to integrate the Avalon Streaming Single Clock FIFO IP (AVST FIFO IP) with the GTS Ethernet Hard IP (GTS EHIP) , but the GTS EHIP outputs signals rxstatus_valid and rxstatus_data, that don't interface with the AVST FIFO IP. The AVST FIFO IP is in a custom module that sits in between the GTS EHIP and the rest of the 1x10G Ethernet System Example Design: Agilex 5 FPGA E-Series Modular Development Kit (Link: https://altera-fpga.github.io/rel-25.3/embedded-designs/agilex-5/e-series/modular/ethernet/agx5e-ethernet-10g/ug-agx5e-ethernet-10g/). How should I handle these signals? Can I ignore them? Is there a example reference design that does this? Thank you for the help! IP Blocks (left:EHIP, right:avst sc fifo ip): SC FIFO Parameters:Error when simulating F-tile Ethernet example design
When running "run_vcsmx.sh" following set of errors occurs Just one example Error-[URMI] Unresolved modules ../ex_200G/sim/../../hardware_test_design/support_logic/eth_f_hw_auto_tiles.sv, 2655 "intfc_m_hdpldadapt_avmm1_mux #(.topology("UX16E400GPTP_XX_DISABLED_XX_DISABLED"), .maib_id(0), .num_ip_on_intfc_00(2), .system_pll_ip_index_on_intfc_00(1), .num_ip_on_intfc_01(2), .system_pll_ip_index_on_intfc_01(1)) z1577b_x0_y0_n0__avmm1_0( .pld_avmm1_busy_real (z1577b_x0_y0_n0__avmm1_0__pld_avmm1_busy_real), .pld_avmm1_clk_rowclk_real (z1577b_x0_y0_n0__avmm1_0__pld_avmm1_clk_rowclk_real), .pld_avmm1_cmdfifo_wr_full_real (z1577b_x0_y0_n0__avmm1_0__pld_avmm1_cmdfifo_wr_full_real), .pld_avmm1_cmdfifo_wr_pfull_real (z1577b_x0_y0_n0__avmm1_0__pld_avmm1_cmdfifo_wr_pfull_real), .pld_avmm1_read_real (z1577b_x0_y0_n0__avmm1_0__pld_avmm1_read_real), .pld_avmm1_readdata_real (z1577b_x0_y0_n0__avmm1_0__pld_avmm1_readdata_real), .pld_avmm1_readdatavalid_rea ... " Module definition of above instance is not found in the design. eth_f_hw_auto_tiles.sv is a 36 MB sv-file, making debugging of this quite tedious. I've only followed the design example user guide which states the script should be able to run out of the box.GTS DirectPHY simple simulation VHDL
Hello everyone, I'm trying to do a simple GTS Direct PHY simulation in VHDL. I've created a simple design in platform designer to try out the GTS transceivers in a serial loopback mode: As one can see, most of the ports are exported to the testbench which handles almost all of them. After asserting i_tx_reset, i_rx_reset and waiting until acknowledge flags go up and deasserting of the resets i_tx_reset and i_rx_reset, I expect that o_tx_ready and o_rx_ready go high. In my case, I see only o_tx_ready is asserted but o_rx_ready not. Using QuestaSim I do the following: set TOP_LEVEL_NAME tb_gts set USER_DEFINED_ELAB_OPTIONS "-t fs" source msim_setup.tcl dev_com com vcom +acc -2008 ../../../tb/tb_gts.vhd elab_debug add wave -position insertpoint sim:/tb_gts/dut/gts_0/* add wave -position insertpoint sim:/tb_gts/dut/s10_user_rst_clkgate_0/* add wave -position insertpoint sim:/tb_gts/dut/gts_reset_seq_0/* run 200 us Quartus version: 26.1 QuestaSim version: 2023.4, 2026.1 The test design is in the attachment. What could lead to such behavior? Any ideas? It must be something I did wrong. Can someone, please, help find out where is the problem? Thank you.
