Agilex-5 supported Transceivers
I am currently evaluating the capabilities of the Altera Dev Board DK-A5E065AB32AEA. As most SFP+ and QSFP+ Transceivers are often vendor-locked, is there a list of qualified Transceivers available? Intel E10GSFPSR and another Xcvr marketed as support for Nvidia did not work in my case, as I attempted to do the initial Testing using BTS App as per document D554638 Which transceivers were used by Intel(Altera) for qualifiying/testing the development board DK-A5E065AB32AEA ?
Stratix 10 fPLL is cascade source mode doesn't lock
Hello everyone. I use fPLL cascading with Stratix 10 FPGA: fPLL in cascade source mode is connected to fPLL in transceiver mode. In my design reference clock for fPLL in cascade source mode is not stable after power-up and I apply user recalibration to it. But after user recalibration when reference clock is stable, fPLL doesn't set lock signal. After some investigation of the issue, I found that my design works fine with Quartus Pro 21.2 but doesn't work with newer versions like Quartus Pro 23.4/25.1/26.1. Is there any known issue about fPLL is cascade source mode? Any suggestions about how to overcome this issue are welcomed.
Queries on 46.6944 Gbps PAM4 F-Tile Configuration and Loopback Testing using Agilex7
Team, Quartus: Quartus Prime Pro 26.1.0 I am currently working on an Agilex 7 F-Tile transceiver configuration for a 46.6944 Gbps PAM4 application. Please find my query (Read file) as attached and provide advise.. Regards amolkumar
Looking for example testbench for Cyclone-V Transceiver Custom_PHY IP from UG-01080-1.7
Hi, I am looking into the Altera Transceiver PHY IP Core User Guide, UG-01080-1.7 (June 2012). I followed section 7, “Custom PHY IP Core” to generate a custom PHY core using the Quartus 23.1-based MegaWizard and IP Catalog for my Cyclone-V FPGA. I have all Verilog files generated for the custom PHY IP in a new folder tst_xcvr_phy_custom. Next, I tried to do a basic loopback simulation of this custom PHY core. Page 7-28 in the user guide states : ............ However when I try the "Altera wiki" link I get .... not sure why I get this, I do have an active Altera account. Perhaps this Altera-Wiki has been migrated to a Github Altera Transceivers (PHY IP) examples repo ? Can someone help me get an example testbench for the Cyclone-V custom PHY IP ? I have QuestaSim and ModelSim for simulating with it.
Problem with alt_2p5g_phy and polarity inversion.
We are using Altera alt_2p5g_phy with a fixed clock of 2.5Ghz. We need rx and tx polarity inversion in our set up. Unfortunately the GUI to set up the phy does not allow to modify the polarity. From the documents of the phy it is clear that this functionality is available. Is there a way to enable the inversion? Thanks in advance for any help.
Agilex 5 GTS Supported Protocols
Hi Altera/Community, I’m trying to better understand the protocols supported by the Agilex 5 GTS transceivers. In the user guide, it mentions that the supported protocol is 10GBase-LR. I wanted to confirm: is 10GBase-R the underlying protocol used before the optical module? Also, does this mean that other optical modules, such as 10GBase-SR, are supported as well? Any clarification on how the transceivers interact with different optical modules would be greatly appreciated. Thanks in advance!Tranceiver Enhanced PCS Basic mode questions
Hello Guys, We used Arria GX and Straitx IV GX devices before, now we switch to use Cyclone 10 GX FPGA. I have several simple questions about XCVR's control port/signal. Why I can't see rx_control and tx_control ports when I make "Enable simplified data interface" ON? In basic or custom mode, 1 bit control signal corresponding 8-bit parallel data bits. I read XCVR user guide, it seems that only LSB 2-bits of the control bus will be used to recognize/indicate data word or control word?
FPGA programming before XCVR's ref clock is ready
Hi, I use F-Tile Agilex 7 and Q24.2. On power cycle (P.C) my reference transceivers clock is not ready and stable, so I do the following reset sequence to the System PLL (created for no stable XCVR's ref clock, attached): When P.C, setting the refclock_ready, en_refclk_fgt_0, en_refclk_fgt_1 to 3'd0, 1'b0, 1'b0, respectively. Stabling the transceiver's input reference clock (loading its config parameters) Setting refclock_ready, en_refclk_fgt_0, en_refclk_fgt_1 to 3'd1, 1'b1, 1'b1, respectively. Then, waiting until refclock_status, refclk_fgt_enabled_0/1 and sys_pll_locked are asserted to 1'b1 Sometimes (not often), one of the statuses on section 4 are not asserted HIGH, and thus I need to do the reset sequence again and since it fails again and again I need to do P.C again. Is there a problem with my reset sequence? Is there a way not to P.C the FPGA and fixing this online? Should I synchronize between the assertion of refclock_ready, en_refclk_fgt_0 and en_refclk_fgt_1? Thanks a lot, Arik
