How to Prevent Agilex 7 F-tile PMA Direct PHY TX Lane Skew

Hi,

We are implementing a 16-lane custom 1.0125 Gbps TX with F-tile PMA Direct PHY IP. The 16 lanes should be bonded together and they need to have a skew of less than 0.05 UI. However, we simulated the TX and found the serial output of each lane had skew of up to 11 ns, despite the fact that they had sychronized parallel input data. We have followed the suggested settings in user guide to enable system bonding, such as Number of Lanes=16, PMA Width=16, and Selected tx_clkout clock source=Bond Clock.

For IP port connection, we use tx_clkout[0] as the source of all 16 tx_coreclkin. We also use it to clock all 16 parallel input data of TX in FPGA core fabric to make sure they are synchronized. 

Our IP Parameter and waveform is as attched. In testbench we feed parallel input data to all 16 lanes at the same time. We also assert TX PMA Interface Data Valid bit [38]. However, the serial output of each lane seems to start at different point of time, creating skew. Is this model behavior or actual hardware behavior? We tested on development board and our target sink is unable to lock to TX serial output as expected. Is there any way to eliminate the skew?

Below is quartus version and our target board.

Quartus Version : 25.3

Target Board : AGIC040R39A2E2VR0

Thanks

wentsung