Forum Discussion
ContributorAvalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset
Dear Intel,
Based on the forum info and datasheet it is allow to use soft reset rather than hard reset.
In order to do so, changing
<parameter name="force_src" value="0" />
to
<parameter name="force_src" value="1" />
Should basically turn the HRC to SRC.
However during actual system test SRC stuck on driver loaded while HRC does not.
According to the above background informations:
1: do SRC allowed in GEN1 PCIe
2: How to properly driven the reset signal under verilog possible example could be good.
Thanks,
Brian
Ok the solution to resolve SRC under Hard PCIe RP:
The example from rocketchip and MitySOM gate the mgmt reset by nreset_status.
Due to pin_perst is not used -> 1'b1
The nreset_status will not release unless mgmt is reset with npor while gating mgmt reset bynreset_status will dead lock and never exit the reset.
9 Replies
BrianSune_FroumHi Altera,
More info:
Based on the STLA, it looks like the reconfiguration calibration never turn low after reset.
While HRC can work without any issue.The SRC simply feed 1'b1 to the pin_perst and please do help or provide instruction to fix this trouble.
Thanks,
Brian
RongY_alteraHi Brian,
By using SRC you're likely to control the npor. If so, you need to pull npor LOW more than 100ms and only release it when PCIe ref clock is stable.
Regards,
Rong
- BrianSune_Froum
Can you read previous posts?
I am not focusing on npor problem
The issue is changing from HRC to SRC introduce stuck or hang on Linux driver load.
Where the HRC case did not have such issue.
Thanks
- BrianSune_Froum
Ok the solution to resolve SRC under Hard PCIe RP:
The example from rocketchip and MitySOM gate the mgmt reset by nreset_status.
Due to pin_perst is not used -> 1'b1
The nreset_status will not release unless mgmt is reset with npor while gating mgmt reset bynreset_status will dead lock and never exit the reset.
