ContributorAvalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset
Dear Intel,
Based on the forum info and datasheet it is allow to use soft reset rather than hard reset.
In order to do so, changing
<parameter name="force_src" value="0" />
to
<parameter name="force_src" value="1" />
Should basically turn the HRC to SRC.
However during actual system test SRC stuck on driver loaded while HRC does not.
According to the above background informations:
1: do SRC allowed in GEN1 PCIe
2: How to properly driven the reset signal under verilog possible example could be good.
Thanks,
Brian
Ok the solution to resolve SRC under Hard PCIe RP:
The example from rocketchip and MitySOM gate the mgmt reset by nreset_status.
Due to pin_perst is not used -> 1'b1
The nreset_status will not release unless mgmt is reset with npor while gating mgmt reset bynreset_status will dead lock and never exit the reset.
