Forum Discussion
Occasional ContributorAgilex 5 Reset Sequencer - Design Assitant reports IPC-40038 violation
Hi,
I am using 2x25Gbit PCS/PMA function only (with FEC) and 2x10Gbit PCS/PMA function only (without FEC) in my Agilex 5 design (device A5ED043AB32AE3V, Quartus Pro 26.1). 25Gbit transceiver are using IO bank 4C while 10Gbit transceivers are using IO bank 1C
There is one reference clock driving the GTS PLL as well as the PMA reference clock input of the Ethernet IP core for both the 25Gbit interface and the 10Gbit interface. They are located in the IO bank of their transceivers.
There is one Reset Sequencer for 25Gbit and 10Gbit each. Quartus compiles the design without errors but the Design Assitant reports a Critical Error "IPC-40038 - Individual bit of Control Unit clock of Reset Sequencer IP can drive only a single instance of Ethernet or PCIE IP"
Basically I followed the Use Case 1 chapter 5.6.1 of the GTS Transceiver PHY User Guide version 2026.03.13. Both PCS/PMA units of each type receive the same o_pma_cu_clk from their Reset Sequencer. In a Quad there is just one or two Ethernet Hard IPs but there are 4 PCS/PMA functions accordig to the same document. Can I safely ignore this Critical Warning, is the Warning wrong or do I miss something?
Thank you
Gerhard
Hi,
I have checked with the internal team. The warning against the rule IPC-40038 can be ignored safely.
Regards
10 Replies
Ash_R_AlteraRegular Contributor
Hi,
As I understand, this Warning is related to port o_pma_cu_clk of the Reset Sequencer IP. Please check if your connection is as per the documentation recommendation.
The pma_cu_clk must be connected to your IPs.
Please review your code once and let us know if you find something.
Regards
GerhardCadekHi,
yes this is also my understanding. But I do not understand why this Critical Warning occurs. I followed the documentation and the block diagram you sent. There is one o_pma_cu_clk clock generated by every of the two Reset Synchronizer circuits as there is one transceiver bank used on every side (M equals to 1 in the block diagram). The two 25Gbit PCS/PMA transceivers are placed in IO bank 4C driven by one Reset Sequencer instance while the two 10 Gbit PCS/PMA transceivers are placed in IO bank 1C. That design compiled without errors but the Design Assistant reports these Critical Warnings.
Unfortunately my design is currently broken. I generated the Triple-Speed Ethernet MAC PCS/PMA with HPS adapter and connected it the EMAC0 of the HPS in my design. Now quartus fails to synthesize the design. This IP core is generated with an erroneous netlist by Quartus 26.1 (see my post here https://community.altera.com/discussions/ip-and-transceiver/triple-speed-ethernet-ip-for-agilex-5-fails-during-quartus-synthesis/355686 )
Enjoy a great time!
Gerhard
- GerhardCadek
Hi,
yes, I am using the IP core exactly this way as shown in the figure. As both PCS/PMA functions reside within the same bank, there is one pma_cu_clk output signal from the Reset Sequencer IP driving both PCS/PMA units.
Regards
Gerhard
- Ash_R_Altera
Hi,
I am confused here a bit. Yes, PCS and PMA can reside in the same bank. But, as you have different banks 4C and 1C on right and left side respectively, there should be two reset sequencer IPs in your design. Each IPs pma_cu_clk port should connect to the PHY IP as shown in the diagram. Is that so in your design?
Regards
- GerhardCadek
Hi,
yes exactly. There are two Reset Sequencer IPs, one for each of the two banks / sides. Each Reset Sequencer IP delivers one pma_cu_clk to the two PCS/PMA units in their IO bank. This follows obviously your and my understanding as well as how I read the documentation. Nevertheless, the Design Assitant reports the IPC-40038 violation with severity level critical. Is it safe to ignore this warning as it seems to be erroneous?
Best regards
Gerhard
- GerhardCadek
Hi,
to speed up things I created a Quartus Archive so you can directly check my source code, the IP core configuration and the Quartus messages. I provide you the file ResetSequencerTest20260730.qar (size approx 4.5Mbyte) as an attachment of this message.
Regards
Gerhard
- GerhardCadek
Hi,
I cannot add the Quartus archive due to unknown reasons. Whenever I tried to add the file I cannot press the "Reply" button.....
- GerhardCadek
Hi,
I put the file onto our web server in a temp directory. You can download it using this link:
https://www.oreganosystems.at/application/files/7217/8539/9980/ResetSequencerTest20260730.qar.zip
Regards
Gerhard
- Ash_R_Altera
Hi,
I have checked with the internal team. The warning against the rule IPC-40038 can be ignored safely.
Regards
- GerhardCadek
Thank you that really helps!
